Searched refs:mask (Results 101 - 125 of 2076) sorted by relevance

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/drivers/net/ethernet/mellanox/mlx5/core/
H A Dmlx5_core.h47 #define mlx5_core_dbg_mask(dev, mask, format, ...) \
49 if ((mask) & mlx5_core_debug_mask) \
/drivers/parport/
H A Dparport_gsc.h106 unsigned char mask,
114 mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable);
116 ctr = (ctr & ~mask) ^ val;
162 unsigned char mask,
171 if (mask & 0x20) {
181 /* Restrict mask and val to control lines. */
182 mask &= wm;
185 return __parport_gsc_frob_control (p, mask, val);
105 __parport_gsc_frob_control(struct parport *p, unsigned char mask, unsigned char val) argument
161 parport_gsc_frob_control(struct parport *p, unsigned char mask, unsigned char val) argument
/drivers/gpu/host1x/hw/
H A Dhost1x01_hardware.h90 unsigned class_id, unsigned offset, unsigned mask)
92 return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
105 static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask) argument
107 return (3 << 28) | (offset << 16) | mask;
89 host1x_opcode_setclass( unsigned class_id, unsigned offset, unsigned mask) argument
H A Dhost1x02_hardware.h89 unsigned class_id, unsigned offset, unsigned mask)
91 return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
104 static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask) argument
106 return (3 << 28) | (offset << 16) | mask;
88 host1x_opcode_setclass( unsigned class_id, unsigned offset, unsigned mask) argument
H A Dhost1x04_hardware.h89 unsigned class_id, unsigned offset, unsigned mask)
91 return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
104 static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask) argument
106 return (3 << 28) | (offset << 16) | mask;
88 host1x_opcode_setclass( unsigned class_id, unsigned offset, unsigned mask) argument
/drivers/mfd/
H A Dmax77686.c137 { .reg_offset = 0, .mask = MAX77686_INT1_PWRONF_MSK, },
138 { .reg_offset = 0, .mask = MAX77686_INT1_PWRONR_MSK, },
139 { .reg_offset = 0, .mask = MAX77686_INT1_JIGONBF_MSK, },
140 { .reg_offset = 0, .mask = MAX77686_INT1_JIGONBR_MSK, },
141 { .reg_offset = 0, .mask = MAX77686_INT1_ACOKBF_MSK, },
142 { .reg_offset = 0, .mask = MAX77686_INT1_ACOKBR_MSK, },
143 { .reg_offset = 0, .mask = MAX77686_INT1_ONKEY1S_MSK, },
144 { .reg_offset = 0, .mask = MAX77686_INT1_MRSTB_MSK, },
146 { .reg_offset = 1, .mask = MAX77686_INT2_140C_MSK, },
147 { .reg_offset = 1, .mask
[all...]
H A Dwm5110-tables.c276 .mask = ARIZONA_MICD_CLAMP_FALL_EINT1
279 .mask = ARIZONA_MICD_CLAMP_RISE_EINT1
281 [ARIZONA_IRQ_GP5_FALL] = { .mask = ARIZONA_GP5_FALL_EINT1 },
282 [ARIZONA_IRQ_GP5_RISE] = { .mask = ARIZONA_GP5_RISE_EINT1 },
283 [ARIZONA_IRQ_JD_FALL] = { .mask = ARIZONA_JD1_FALL_EINT1 },
284 [ARIZONA_IRQ_JD_RISE] = { .mask = ARIZONA_JD1_RISE_EINT1 },
301 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
302 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
303 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
304 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask
[all...]
/drivers/misc/ibmasm/
H A Dlowlevel.h65 static inline void ibmasm_enable_interrupts(void __iomem *base_address, int mask) argument
68 writel( readl(ctrl_reg) & ~mask, ctrl_reg);
71 static inline void ibmasm_disable_interrupts(void __iomem *base_address, int mask) argument
74 writel( readl(ctrl_reg) | mask, ctrl_reg);
/drivers/net/ethernet/cisco/enic/
H A Dvnic_intr.h40 u32 mask; /* 0x20 */ member in struct:vnic_intr_ctrl
56 iowrite32(0, &intr->ctrl->mask);
61 iowrite32(1, &intr->ctrl->mask);
66 return ioread32(&intr->ctrl->mask);
/drivers/pcmcia/
H A Dsa11xx_base.h69 #define MECR_SET(mecr, sock, shift, mask, bs) \
70 ((mecr)=((mecr)&~(((mask)<<(shift))<<\
74 #define MECR_GET(mecr, sock, shift, mask) \
76 (shift))&(mask))
/drivers/staging/comedi/
H A Dcomedilib.h29 unsigned int mask, unsigned int *bits,
/drivers/staging/lustre/include/linux/libcfs/
H A Dlibcfs_cpu.h94 /* cpu mask */
96 /* node mask */
164 * add all cpus in \a mask to CPU partition \a cpt
168 int cpt, cpumask_t *mask);
170 * remove all cpus in \a mask from CPU partition \a cpt
173 int cpt, cpumask_t *mask);
185 * add all cpus in node mask \a mask to CPU partition \a cpt
189 int cpt, nodemask_t *mask);
191 * remove all cpus in node mask \
[all...]
/drivers/usb/chipidea/
H A Dotg.c29 * @mask: bitfield mask
31 u32 hw_read_otgsc(struct ci_hdrc *ci, u32 mask) argument
33 return hw_read(ci, OP_OTGSC, mask);
38 * @mask: bitfield mask
41 void hw_write_otgsc(struct ci_hdrc *ci, u32 mask, u32 data) argument
43 hw_write(ci, OP_OTGSC, mask | OTGSC_INT_STATUS_BITS, data);
/drivers/ata/
H A Dpata_hpt366.c201 static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask) argument
205 mask &= ~ATA_MASK_UDMA;
207 mask &= ~(0xF8 << ATA_SHIFT_UDMA);
209 mask &= ~(0xF0 << ATA_SHIFT_UDMA);
211 mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
213 return mask;
236 u32 mask, reg, t; local
238 /* determine timing mask and find matching clock entry */
240 mask = 0xc1f8ffff;
242 mask
[all...]
/drivers/clocksource/
H A Dmmio.c30 return ~(cycle_t)readl_relaxed(to_mmio_clksrc(c)->reg) & c->mask;
40 return ~(cycle_t)readw_relaxed(to_mmio_clksrc(c)->reg) & c->mask;
69 cs->clksrc.mask = CLOCKSOURCE_MASK(bits);
/drivers/edac/
H A Dedac_core.h389 u8 mask)
391 if (mask != 0xff) {
395 value &= mask;
396 buf &= ~mask;
405 u16 value, u16 mask)
407 if (mask != 0xffff) {
411 value &= mask;
412 buf &= ~mask;
423 * a mask parameter. If mask i
388 pci_write_bits8(struct pci_dev *pdev, int offset, u8 value, u8 mask) argument
404 pci_write_bits16(struct pci_dev *pdev, int offset, u16 value, u16 mask) argument
428 pci_write_bits32(struct pci_dev *pdev, int offset, u32 value, u32 mask) argument
[all...]
/drivers/gpu/drm/nouveau/core/subdev/devinit/
H A Dnv20.c35 uint32_t mask = (device->chipset >= 0x25 ? 0x300 : 0x900); local
49 nv_mask(priv, NV04_PFB_CFG0, 0, mask);
58 nv_mask(priv, NV04_PFB_CFG0, mask, 0);
/drivers/iommu/
H A Domap-iopgtable.h14 * "L2 table" address mask and size definitions.
21 * "section" address mask and size definitions.
28 * "supersection" address mask and size definitions.
38 * "small page" address mask and size definitions.
45 * "large page" address mask and size definitions.
60 * @mask: omap iommu descriptor mask
64 static inline phys_addr_t omap_iommu_translate(u32 d, u32 va, u32 mask) argument
66 return (d & mask) | (va & (~mask));
[all...]
/drivers/media/dvb-frontends/
H A Dstv6110x_priv.h49 #define STV6110x_SETFIELD(mask, bitf, val) \
50 (mask = (mask & (~(((1 << STV6110x_WIDTH_##bitf) - 1) << \
/drivers/media/pci/cx18/
H A Dcx18-gpio.c69 static void gpio_update(struct cx18 *cx, u32 mask, u32 data) argument
71 if (mask == 0)
75 cx->gpio_val = (cx->gpio_val & ~mask) | (data & mask);
84 u32 mask; local
86 mask = active_lo | active_hi;
87 if (mask == 0)
97 gpio_update(cx, mask, ~active_lo);
101 gpio_update(cx, mask, ~active_hi);
128 gpio_update(cx, cx->card->gpio_audio_input.mask,
[all...]
/drivers/media/rc/img-ir/
H A Dimg-ir-jvc.c39 cust_m = (in->mask >> 8) & 0xff;
41 data_m = (in->mask >> 0) & 0xff;
44 out->mask = cust_m | data_m << 8;
H A Dimg-ir-sharp.c48 addr_m = (in->mask >> 8) & 0x1f;
50 cmd_m = (in->mask >> 0) & 0xff;
63 out->mask = addr_m |
/drivers/staging/comedi/drivers/
H A D8255.c114 unsigned int mask; local
117 mask = comedi_dio_update_state(s, data);
118 if (mask) {
119 if (mask & 0xff)
122 if (mask & 0xff00)
125 if (mask & 0xff0000)
166 unsigned int mask; local
170 mask = 0x0000ff;
172 mask = 0x00ff00;
174 mask
[all...]
/drivers/video/fbdev/omap2/dss/
H A Ddispc-compat.c47 u32 mask; member in struct:omap_dispc_isr_data
131 u32 mask; local
135 mask = dispc_compat.irq_error_mask;
143 mask |= isr_data->mask;
146 dispc_write_irqenable(mask);
149 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask) argument
165 isr_data->mask == mask) {
182 isr_data->mask
203 omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask) argument
462 dispc_mgr_disable_isr(void *data, u32 mask) argument
512 dispc_digit_out_enable_isr(void *data, u32 mask) argument
637 dispc_irq_wait_handler(void *data, u32 mask) argument
[all...]
/drivers/watchdog/
H A Dkempld_wdt.c78 u32 mask; member in struct:kempld_wdt_stage
119 if (!stage || !stage->mask)
157 if (stage_timeout64 > stage->mask)
160 stage_timeout = stage_timeout64 & stage->mask;
187 if (!stage->mask)
194 stage_timeout = (stage_timeout & stage->mask) * prescaler;
216 if (pretimeout_stage->mask && wdt_data->pretimeout > 0)
242 if (!pretimeout_stage->mask)
377 u32 mask; local
383 pretimeout_stage->mask
[all...]

Completed in 1643 milliseconds

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