Searched refs:mask (Results 176 - 200 of 2076) sorted by relevance

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/drivers/media/rc/img-ir/
H A Dimg-ir-sony.c65 dev_m = (in->mask >> 16) & 0xff;
67 subdev_m = (in->mask >> 8) & 0xff;
69 func_m = (in->mask >> 0) & 0x7f;
88 * The hardware mask cannot distinguish high device bits and low
104 out->mask = func_m |
/drivers/net/ethernet/arc/
H A Demac.h182 * arc_reg_or - Applies mask to specified EMAC register - ("reg" | "mask").
185 * @mask: Mask to apply to specified register.
187 * This function reads initial register value, then applies provided mask
190 static inline void arc_reg_or(struct arc_emac_priv *priv, int reg, int mask) argument
193 arc_reg_set(priv, reg, value | mask);
197 * arc_reg_clr - Applies mask to specified EMAC register - ("reg" & ~"mask").
200 * @mask: Mask to apply to specified register.
202 * This function reads initial register value, then applies provided mask
205 arc_reg_clr(struct arc_emac_priv *priv, int reg, int mask) argument
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/drivers/net/wireless/rtlwifi/
H A Dcore.h42 u32 mask, u32 data);
/drivers/staging/line6/
H A Dmidibuf.h33 unsigned short mask);
/drivers/staging/lustre/lustre/libcfs/
H A Dlibcfs_cpu.c128 cfs_cpt_set_cpumask(struct cfs_cpt_table *cptab, int cpt, cpumask_t *mask) argument
135 cfs_cpt_unset_cpumask(struct cfs_cpt_table *cptab, int cpt, cpumask_t *mask) argument
154 cfs_cpt_set_nodemask(struct cfs_cpt_table *cptab, int cpt, nodemask_t *mask) argument
161 cfs_cpt_unset_nodemask(struct cfs_cpt_table *cptab, int cpt, nodemask_t *mask) argument
/drivers/gpu/drm/sti/
H A Dsti_mixer.c40 /* mask in CTL reg */
106 u32 mask, val; local
134 mask = GAM_DEPTH_MASK_ID << (3 * depth);
139 dev_dbg(mixer->dev, "GAM_MIXER_CRB val 0x%x mask 0x%x\n",
140 layer_id, mask);
143 val &= ~mask;
199 u32 mask, val; local
204 mask = sti_mixer_get_layer_mask(layer);
205 if (!mask) {
206 DRM_ERROR("Can not find layer mask\
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/drivers/ssb/
H A Ddriver_chipcommon.c33 u32 mask, u32 value)
35 value &= mask;
36 value |= chipco_read32(cc, offset) & ~mask;
494 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value) argument
496 chipco_write32_masked(cc, SSB_CHIPCO_IRQMASK, mask, value);
499 u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask) argument
501 return chipco_read32(cc, SSB_CHIPCO_IRQSTAT) & mask;
504 u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask) argument
506 return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
509 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u3 argument
32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset, u32 mask, u32 value) argument
521 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value) argument
533 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value) argument
546 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value) argument
558 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value) argument
570 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value) argument
585 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value) argument
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/drivers/media/pci/dm1105/
H A Ddm1105.c212 u32 mask, off, v13, v18; member in struct:dm1105_board::__anon2231
227 .mask = DM1105_LNB_MASK,
236 .mask = DM1105_LNB_MASK,
245 .mask = DM1105_LNB_MASK,
254 .mask = DM05_LNB_MASK,
263 .mask = UNBR_LNB_MASK,
385 #define dm_andorl(reg, mask, value) \
386 outl((inl(dm_io_mem(reg)) & ~(mask)) |\
387 ((value) & (mask)), (dm_io_mem(reg)))
396 static void dm1105_gpio_set(struct dm1105_dev *dev, u32 mask) argument
406 dm1105_gpio_clear(struct dm1105_dev *dev, u32 mask) argument
416 dm1105_gpio_andor(struct dm1105_dev *dev, u32 mask, u32 val) argument
426 dm1105_gpio_get(struct dm1105_dev *dev, u32 mask) argument
437 dm1105_gpio_enable(struct dm1105_dev *dev, u32 mask, int asoutput) argument
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/drivers/mfd/
H A Dstmpe.c62 static int __stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val) argument
70 ret &= ~mask;
179 * @mask: Mask of bits to set
182 int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val) argument
187 ret = __stmpe_set_bits(stmpe, reg, mask, val);
251 int mask = (1 << af_bits) - 1; local
276 regs[regoffset] &= ~(mask << pos);
457 unsigned int mask = 0; local
460 mask |= STMPE811_SYS_CTRL2_GPIO_OFF;
463 mask |
605 unsigned int mask = 0; local
690 unsigned int mask = 0; local
775 unsigned int mask = 0; local
935 int mask = 1 << (offset % 8); local
945 int mask = 1 << (offset % 8); local
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/drivers/ata/
H A Dpata_hpt37x.c284 static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask) argument
288 mask &= ~ATA_MASK_UDMA;
290 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
292 return mask;
302 static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask) argument
306 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
308 return mask;
314 * @mask: mode mask
319 static unsigned long hpt372_filter(struct ata_device *adev, unsigned long mask) argument
415 u32 reg, timing, mask; local
509 u32 reg, timing, mask; local
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H A Dpata_acpi.c25 unsigned long mask[2]; member in struct:pata_acpi
57 if ((acpi->mask[0] | acpi->mask[1]) & (0xF8 << ATA_SHIFT_UDMA))
66 * @mask: proposed modes
69 * set up sensibly. From this we get a mask of ACPI modes we can use
93 * @mask: mask of valid modes
99 static unsigned long pacpi_mode_filter(struct ata_device *adev, unsigned long mask) argument
102 return mask & acpi->mask[ade
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/drivers/clocksource/
H A Dsamsung_pwm_timer.c237 u32 mask = (1 << pwm.event_id); local
238 writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
256 u32 mask = (1 << pwm.event_id); local
257 writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
294 u32 mask = (1 << pwm.event_id); local
295 writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
363 samsung_clocksource.mask
388 u8 mask; local
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/drivers/iio/pressure/
H A Dst_pressure_core.c188 .mask = ST_PRESS_LPS331AP_ODR_MASK,
198 .mask = ST_PRESS_LPS331AP_PW_MASK,
204 .mask = ST_PRESS_LPS331AP_FS_MASK,
216 .mask = ST_PRESS_LPS331AP_BDU_MASK,
235 .mask = ST_PRESS_LPS001WP_ODR_MASK,
244 .mask = ST_PRESS_LPS001WP_PW_MASK,
253 .mask = ST_PRESS_LPS001WP_BDU_MASK,
270 .mask = ST_PRESS_LPS25H_ODR_MASK,
280 .mask = ST_PRESS_LPS25H_PW_MASK,
286 .mask
310 st_press_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *ch, int val, int val2, long mask) argument
331 st_press_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *ch, int *val, int *val2, long mask) argument
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/drivers/pwm/
H A Dpwm-twl.c168 u8 val, mask, bits; local
171 mask = TWL4030_GPIO7_VIBRASYNC_PWM1_MASK;
174 mask = TWL4030_GPIO6_PWM0_MUTE_MASK;
186 twl->twl4030_pwm_mux &= ~mask;
187 twl->twl4030_pwm_mux |= (val & mask);
190 val &= ~mask;
206 u8 val, mask; local
209 mask = TWL4030_GPIO7_VIBRASYNC_PWM1_MASK;
211 mask = TWL4030_GPIO6_PWM0_MUTE_MASK;
221 val &= ~mask;
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/drivers/gpu/drm/nouveau/core/subdev/fb/
H A Dramnve0.c147 nve0_ram_train(struct nve0_ramfuc *fuc, u32 mask, u32 data) argument
152 ram_mask(fuc, 0x10f910, mask, data);
153 ram_mask(fuc, 0x10f914, mask, data);
241 u32 mask = _mask | _copy; local
248 u32 next = (prev & ~mask) | data;
264 u32 mask, data; local
308 mask = 0x800f07e0;
331 mask |= 0x03000000;
333 mask |= 0x00002000;
335 mask |
693 u32 mask, data; local
1081 u32 mask, data; local
1181 u16 mask; member in struct:nve0_ram_train
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/drivers/media/rc/
H A Dwinbond-cir.c147 /* Select mask register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
260 wbcir_set_bits(unsigned long addr, u8 bits, u8 mask) argument
265 val = ((val & ~mask) | (bits & mask));
612 wbcir_txmask(struct rc_dev *dev, u32 mask) argument
619 switch (mask) {
642 if (data->txmask != mask) {
644 data->txmask = mask;
699 u8 mask[11]; local
704 memset(mask,
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/drivers/acpi/acpica/
H A Drsutils.c56 * PARAMETERS: mask - Bitmask to decode
61 * DESCRIPTION: Convert a bit mask into a list of values
64 u8 acpi_rs_decode_bitmask(u16 mask, u8 * list) argument
71 /* Decode the mask bits */
73 for (i = 0, bit_count = 0; mask; i++) {
74 if (mask & 0x0001) {
79 mask >>= 1;
101 u16 mask; local
107 for (i = 0, mask = 0; i < count; i++) {
108 mask |
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/drivers/bcma/
H A Ddriver_chipcommon_b.c14 static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask, argument
22 if ((val & mask) == value)
/drivers/crypto/ux500/hash/
H A Dhash_alg.h98 #define HASH_SET_BITS(reg_name, mask) \
99 writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
101 #define HASH_CLEAR_BITS(reg_name, mask) \
102 writel_relaxed((readl_relaxed(reg_name) & ~mask), reg_name)
104 #define HASH_PUT_BITS(reg, val, shift, mask) \
105 writel_relaxed(((readl(reg) & ~(mask)) | \
106 (((u32)val << shift) & (mask))), reg)
301 * @mask: DMA capabilities bitmap mask.
310 dma_cap_mask_t mask; member in struct:hash_dma
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/drivers/gpu/drm/nouveau/core/include/subdev/bios/
H A Ddp.h6 u16 mask; member in struct:nvbios_dpout
15 u16 nvbios_dpout_match(struct nouveau_bios *, u16 type, u16 mask,
/drivers/gpu/drm/nouveau/core/subdev/i2c/
H A Dnve0.c42 nve0_aux_mask(struct nouveau_i2c *i2c, u32 type, u32 mask, u32 data) argument
46 if (mask & (1 << i)) {
/drivers/gpu/drm/nouveau/core/subdev/ltc/
H A Dgf100.c103 u32 mask; local
105 mask = nv_rd32(priv, 0x00017c);
106 while (mask) {
107 u32 lts, ltc = __ffs(mask);
110 mask &= ~(1 << ltc);
197 u32 parts, mask; local
206 mask = nv_rd32(priv, 0x022554);
208 if (!(mask & (1 << i)))
/drivers/gpu/host1x/hw/
H A Ddebug_hw.c43 unsigned mask; local
48 mask = val & 0x3f;
49 if (mask) {
50 host1x_debug_output(o, "SETCL(class=%03x, offset=%03x, mask=%02x, [",
52 val >> 16 & 0xfff, mask);
53 return hweight8(mask);
71 mask = val & 0xffff;
72 host1x_debug_output(o, "MASK(offset=%03x, mask=%03x, [",
73 val >> 16 & 0xfff, mask);
74 return hweight16(mask);
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/drivers/infiniband/hw/cxgb3/
H A Diwch_mem.c142 u64 mask; local
145 mask = 0;
155 mask |= buffer_list[i].addr;
157 mask |= buffer_list[i].addr & PAGE_MASK;
159 mask |= buffer_list[i].addr + buffer_list[i].size;
161 mask |= (buffer_list[i].addr + buffer_list[i].size +
170 if ((1ULL << *shift) & mask)
196 PDBG("%s va 0x%llx mask 0x%llx shift %d len %lld pbl_size %d\n",
198 (unsigned long long) mask, *shift, (unsigned long long) *total_size,
/drivers/irqchip/
H A Dirq-keystone.c38 u32 mask; member in struct:keystone_irq_device
70 kirq->mask |= BIT(d->hwirq);
71 dev_dbg(kirq->dev, "mask %lu [%x]\n", d->hwirq, kirq->mask);
78 kirq->mask &= ~BIT(d->hwirq);
79 dev_dbg(kirq->dev, "unmask %lu [%x]\n", d->hwirq, kirq->mask);
100 dev_dbg(kirq->dev, "pending 0x%lx, mask 0x%x\n", pending, kirq->mask);
102 pending = (pending >> BIT_OFS) & ~kirq->mask;
104 dev_dbg(kirq->dev, "pending after mask
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