Searched refs:mask (Results 26 - 50 of 2076) sorted by relevance

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/drivers/crypto/ux500/cryp/
H A Dcryp_p.h23 #define CRYP_SET_BITS(reg_name, mask) \
24 writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
26 #define CRYP_WRITE_BIT(reg_name, val, mask) \
27 writel_relaxed(((readl_relaxed(reg_name) & ~(mask)) |\
28 ((val) & (mask))), reg_name)
33 #define CRYP_PUT_BITS(reg, val, shift, mask) \
34 writel_relaxed(((readl_relaxed(reg) & ~(mask)) | \
35 (((u32)val << shift) & (mask))), reg)
66 * CRYP Control register specific mask
/drivers/mfd/
H A Das3722.c85 .mask = AS3722_INTERRUPT_MASK1_LID,
88 .mask = AS3722_INTERRUPT_MASK1_ACOK,
91 .mask = AS3722_INTERRUPT_MASK1_ENABLE1,
94 .mask = AS3722_INTERRUPT_MASK1_OCURR_ALARM_SD0,
97 .mask = AS3722_INTERRUPT_MASK1_ONKEY_LONG,
100 .mask = AS3722_INTERRUPT_MASK1_ONKEY,
103 .mask = AS3722_INTERRUPT_MASK1_OVTMP,
106 .mask = AS3722_INTERRUPT_MASK1_LOWBAT,
111 .mask = AS3722_INTERRUPT_MASK2_SD0_LV,
115 .mask
[all...]
H A D88pm805.c92 .mask = PM805_INT1_HP1_SHRT,
95 .mask = PM805_INT1_HP2_SHRT,
98 .mask = PM805_INT1_MIC_CONFLICT,
101 .mask = PM805_INT1_CLIP_FAULT,
104 .mask = PM805_INT1_LDO_OFF,
107 .mask = PM805_INT1_SRC_DPLL_LOCK,
112 .mask = PM805_INT2_MIC_DET,
116 .mask = PM805_INT2_SHRT_BTN_DET,
120 .mask = PM805_INT2_VOLM_BTN_DET,
124 .mask
140 int data, mask, ret = -EINVAL; local
[all...]
H A Dmax77693.c62 { .mask = LED_IRQ_FLED2_OPEN, },
63 { .mask = LED_IRQ_FLED2_SHORT, },
64 { .mask = LED_IRQ_FLED1_OPEN, },
65 { .mask = LED_IRQ_FLED1_SHORT, },
66 { .mask = LED_IRQ_MAX_FLASH, },
80 { .mask = TOPSYS_IRQ_T120C_INT, },
81 { .mask = TOPSYS_IRQ_T140C_INT, },
82 { .mask = TOPSYS_IRQ_LOWSYS_INT, },
96 { .mask = CHG_IRQ_BYP_I, },
97 { .mask
[all...]
H A Dmax8998-irq.c22 int mask; member in struct:max8998_irq_data
28 .mask = MAX8998_IRQ_DCINF_MASK,
32 .mask = MAX8998_IRQ_DCINR_MASK,
36 .mask = MAX8998_IRQ_JIGF_MASK,
40 .mask = MAX8998_IRQ_JIGR_MASK,
44 .mask = MAX8998_IRQ_PWRONF_MASK,
48 .mask = MAX8998_IRQ_PWRONR_MASK,
52 .mask = MAX8998_IRQ_WTSREVNT_MASK,
56 .mask = MAX8998_IRQ_SMPLEVNT_MASK,
60 .mask
[all...]
H A Dtps65910.c60 .mask = INT_MSK_PWRHOLD_F_IT_MSK_MASK,
64 .mask = INT_MSK_VMBHI_IT_MSK_MASK,
68 .mask = INT_MSK_PWRON_IT_MSK_MASK,
72 .mask = INT_MSK_PWRON_LP_IT_MSK_MASK,
76 .mask = INT_MSK_PWRHOLD_R_IT_MSK_MASK,
80 .mask = INT_MSK_HOTDIE_IT_MSK_MASK,
84 .mask = INT_MSK_RTC_ALARM_IT_MSK_MASK,
88 .mask = INT_MSK_RTC_PERIOD_IT_MSK_MASK,
94 .mask = INT_MSK2_GPIO0_R_IT_MSK_MASK,
98 .mask
[all...]
H A Dtps65218.c82 * tps65218_update_bits: Modify bits w.r.t mask, val and level.
86 * @mask: Mask.
91 unsigned int mask, unsigned int val, unsigned int level)
102 data &= ~mask;
103 data |= val & mask;
115 unsigned int mask, unsigned int val, unsigned int level)
117 return tps65218_update_bits(tps, reg, mask, val, level);
122 unsigned int mask, unsigned int level)
124 return tps65218_update_bits(tps, reg, mask, 0, level);
137 .mask
90 tps65218_update_bits(struct tps65218 *tps, unsigned int reg, unsigned int mask, unsigned int val, unsigned int level) argument
114 tps65218_set_bits(struct tps65218 *tps, unsigned int reg, unsigned int mask, unsigned int val, unsigned int level) argument
121 tps65218_clear_bits(struct tps65218 *tps, unsigned int reg, unsigned int mask, unsigned int level) argument
[all...]
/drivers/usb/chipidea/
H A Dotg.h14 u32 hw_read_otgsc(struct ci_hdrc *ci, u32 mask);
15 void hw_write_otgsc(struct ci_hdrc *ci, u32 mask, u32 data);
/drivers/gpu/drm/nouveau/core/subdev/timer/
H A Dbase.c28 nouveau_timer_wait_eq(void *obj, u64 nsec, u32 addr, u32 mask, u32 data) argument
36 if ((nv_rd32(obj, addr) & mask) == data)
39 if ((nv_ro32(obj, addr) & mask) == data)
48 nouveau_timer_wait_ne(void *obj, u64 nsec, u32 addr, u32 mask, u32 data) argument
56 if ((nv_rd32(obj, addr) & mask) != data)
59 if ((nv_ro32(obj, addr) & mask) != data)
/drivers/scsi/aic7xxx/
H A Daic7xxx.reg107 mask STIMESEL 0x18
132 mask PHASE_MASK CDI|IOI|MSGI
133 mask P_DATAOUT 0x00
134 mask P_DATAIN IOI
135 mask P_DATAOUT_DT P_DATAOUT|MSGI
136 mask P_DATAIN_DT P_DATAIN|MSGI
137 mask P_COMMAND CDI
138 mask P_MESGOUT CDI|MSGI
139 mask P_STATUS CDI|IOI
140 mask P_MESGI
[all...]
/drivers/infiniband/hw/ehca/
H A Dehca_tools.h132 #define EHCA_BMASK_SHIFTPOS(mask) (((mask) >> 16) & 0xffff)
135 #define EHCA_BMASK_MASK(mask) (~0ULL >> ((64 - (mask)) & 0xffff))
138 * EHCA_BMASK_SET - return value shifted and masked by mask
140 * variable&=~EHCA_BMASK_SET(MY_MASK,-1) clears the bits from the mask
143 #define EHCA_BMASK_SET(mask, value) \
144 ((EHCA_BMASK_MASK(mask) & ((u64)(value))) << EHCA_BMASK_SHIFTPOS(mask))
147 * EHCA_BMASK_GET - extract a parameter from value by mask
[all...]
/drivers/pinctrl/spear/
H A Dpinctrl-spear320.c37 .mask = 0x00000007,
45 .mask = 0x00000007,
53 .mask = 0x00000007,
61 .mask = 0x00000007,
69 .mask = 0x00000001,
466 .mask = PMX_PL_69_MASK,
470 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
478 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
484 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
523 .mask
[all...]
H A Dpinctrl-spear1340.c220 .mask = PADS_AS_GPIO_REG0_MASK,
224 .mask = PADS_AS_GPIO_REGS_MASK,
228 .mask = PADS_AS_GPIO_REGS_MASK,
232 .mask = PADS_AS_GPIO_REGS_MASK,
236 .mask = PADS_AS_GPIO_REGS_MASK,
240 .mask = PADS_AS_GPIO_REGS_MASK,
244 .mask = PADS_AS_GPIO_REGS_MASK,
248 .mask = PADS_AS_GPIO_REG7_MASK,
281 .mask = FSMC_8BIT_REG7_MASK,
306 .mask
[all...]
/drivers/gpu/drm/nouveau/core/engine/perfmon/
H A Dnve0.c107 u32 mask; local
128 mask = (1 << nv_rd32(priv, 0x022430)) - 1;
129 mask &= ~nv_rd32(priv, 0x022504);
130 mask &= ~nv_rd32(priv, 0x022584);
132 ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000,
138 mask = (1 << nv_rd32(priv, 0x022438)) - 1;
139 mask &= ~nv_rd32(priv, 0x022548);
140 mask &= ~nv_rd32(priv, 0x0225c8);
142 ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000,
/drivers/video/fbdev/
H A Datafb_iplan2p8.c114 u32 pval[4], v, v1, mask; local
120 mask = 0xff00ff00;
135 pval[0] = (*src32++ << 8) & mask;
136 pval[1] = (*src32++ << 8) & mask;
137 pval[2] = (*src32++ << 8) & mask;
138 pval[3] = (*src32++ << 8) & mask;
140 pval[0] = dst32[0] & mask;
141 pval[1] = dst32[1] & mask;
142 pval[2] = dst32[2] & mask;
143 pval[3] = dst32[3] & mask;
177 u32 pval[4], v, v1, mask; local
[all...]
/drivers/input/joystick/
H A Danalog.c115 int mask; member in struct:analog
124 unsigned char mask; member in struct:analog_port
207 if (analog->mask & ANALOG_HAT_FCS)
215 if (analog->mask & (0x10 << i))
218 if (analog->mask & ANALOG_HBTN_CHF)
222 if (analog->mask & ANALOG_BTN_TL)
224 if (analog->mask & ANALOG_BTN_TR)
226 if (analog->mask & ANALOG_BTN_TL2)
228 if (analog->mask & ANALOG_BTN_TR2)
232 if (analog->mask
[all...]
/drivers/infiniband/hw/qib/
H A Dqib_twsi.c91 u32 mask; local
95 mask = 1UL << dd->gpio_scl_num;
98 dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask);
109 if (mask & dd->f_gpio_mod(dd, 0, 0, 0))
122 u32 mask; local
124 mask = 1UL << dd->gpio_sda_num;
127 dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask);
136 u32 read_val, mask; local
266 u32 pins, mask; local
[all...]
/drivers/staging/lustre/include/linux/libcfs/
H A Dlibcfs_debug.h60 int libcfs_debug_mask2str(char *str, int size, int mask, int is_subsys);
61 int libcfs_debug_str2mask(int *mask, const char *str, int is_subsys);
182 #define LIBCFS_DEBUG_MSG_DATA_INIT(data, mask, cdls) \
189 (data)->msg_mask = (mask); \
192 #define LIBCFS_DEBUG_MSG_DATA_DECL(dataname, mask, cdls) \
199 dataname.msg_mask = (mask);
202 * Filters out logging messages based on mask and subsystem.
204 static inline int cfs_cdebug_show(unsigned int mask, unsigned int subsystem) argument
206 return mask & D_CANTMASK ||
207 ((libcfs_debug & mask)
[all...]
/drivers/gpu/drm/nouveau/core/subdev/gpio/
H A Dnv94.c41 nv94_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data) argument
46 inte0 = (inte0 & ~(mask << 16)) | (data << 16);
48 inte0 = (inte0 & ~(mask & 0xffff)) | (data & 0xffff);
49 mask >>= 16;
52 inte1 = (inte1 & ~(mask << 16)) | (data << 16);
54 inte1 = (inte1 & ~mask) | data;
H A Dnve0.c41 nve0_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data) argument
46 inte0 = (inte0 & ~(mask << 16)) | (data << 16);
48 inte0 = (inte0 & ~(mask & 0xffff)) | (data & 0xffff);
49 mask >>= 16;
52 inte1 = (inte1 & ~(mask << 16)) | (data << 16);
54 inte1 = (inte1 & ~mask) | data;
H A Dnv10.c54 u32 reg, mask, data; local
59 mask = 0x00000011;
65 mask = 0x00000003;
71 mask = 0x00000003;
77 nv_mask(gpio, reg, mask << line, data << line);
92 nv10_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data) argument
96 inte = (inte & ~(mask << 16)) | (data << 16);
98 inte = (inte & ~mask) | data;
/drivers/pcmcia/
H A Dsa1100_assabet.c44 unsigned int mask; local
48 mask = 0;
56 mask = ASSABET_BCR_CF_PWR;
68 mask |= ASSABET_BCR_CF_RST;
70 mask |= ASSABET_BCR_CF_BUS_OFF;
73 ASSABET_BCR_CF_BUS_OFF, mask);
/drivers/gpu/drm/nouveau/core/core/
H A Denum.c58 if (value & bf->mask) {
60 value &= ~bf->mask;
/drivers/gpu/drm/nouveau/core/subdev/fb/
H A Dramfuc.h17 u32 mask; member in struct:ramfuc_reg
22 ramfuc_stride(u32 addr, u32 stride, u32 mask) argument
28 .mask = mask,
40 .mask = 0x3,
52 .mask = 0x1,
94 unsigned int mask, off = 0; local
99 for (mask = reg->mask; mask >
115 ramfuc_mask(struct ramfuc *ram, struct ramfuc_reg *reg, u32 mask, u32 data) argument
126 ramfuc_wait(struct ramfuc *ram, u32 addr, u32 mask, u32 data, u32 nsec) argument
[all...]
/drivers/leds/
H A Dleds-syscon.c41 * @mask: the bit in the register corresponding to the LED
48 u32 mask; member in struct:syscon_led
64 val = sled->mask;
68 ret = regmap_update_bits(sled->map, sled->offset, sled->mask, val);
123 if (of_property_read_u32(child, "mask", &sled->mask))
138 sled->state = !!(val & sled->mask);
142 sled->mask,
143 sled->mask);
149 sled->mask,
[all...]

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