/drivers/video/fbdev/aty/ |
H A D | radeon_base.c | 439 rinfo->pll.ref_clk = (*val) / 10; 443 rinfo->pll.sclk = (*val) / 10; 447 rinfo->pll.mclk = (*val) / 10; 583 rinfo->pll.ref_clk = xtal; 584 rinfo->pll.ref_div = ref_div; 585 rinfo->pll.sclk = sclk; 586 rinfo->pll.mclk = mclk; 604 rinfo->pll.ppll_max = 35000; 605 rinfo->pll.ppll_min = 12000; 606 rinfo->pll [all...] |
H A D | atyfb_base.c | 310 static int pll; variable 373 int pll, mclk, xclk, ecp_max; member in struct:__anon7084 446 par->pll_limits.pll_max = aty_chips[i].pll; 574 par->pll.ct.xres = 0; 578 par->pll.ct.xres = var->xres; 1321 var->bits_per_pixel, &par->pll); 1340 par->dac_ops->set_dac(info, &par->pll, 1342 par->pll_ops->set_pll(info, &par->pll); 1346 pixclock_in_ps = par->pll_ops->pll_to_var(info, &par->pll); 1473 /* dump non shadow CRTC, pll, LC 1534 union aty_pll pll; local 1856 union aty_pll *pll = &par->pll; local 1881 union aty_pll *pll = &par->pll; local [all...] |
/drivers/media/radio/ |
H A D | tef6862.c | 108 u16 pll; local 116 pll = 1964 + ((freq - TEF6862_LO_FREQ) * 20) / FREQ_MUL; 118 i2cmsg[1] = (pll >> 8) & 0xff; 119 i2cmsg[2] = pll & 0xff;
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/drivers/gpu/drm/nouveau/core/subdev/clock/ |
H A D | nv40.c | 27 #include <subdev/bios/pll.h> 29 #include "pll.h" 134 struct nvbios_pll pll; local 137 ret = nvbios_pll_parse(bios, reg, &pll); 141 if (clk < pll.vco1.max_freq) 142 pll.vco2.max_freq = 0; 144 ret = nv04_pll_calc(nv_subdev(priv), &pll, clk, N1, M1, N2, M2, log2P); 173 /* use the second pll for shader/rop clock, if it differs from core */
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H A D | nvaa.c | 27 #include <subdev/bios/pll.h> 32 #include "pll.h" 167 struct nvbios_pll pll; local 171 ret = nvbios_pll_parse(bios, reg, &pll); 175 pll.vco2.max_freq = 0; 176 pll.refclk = clk->read(clk, nv_clk_src_href); 177 if (!pll.refclk) 180 return nv04_pll_calc(nv_subdev(priv), &pll, clock, N, M, NULL, NULL, P);
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H A D | nvc0.c | 27 #include <subdev/bios/pll.h> 30 #include "pll.h" 59 read_pll(struct nvc0_clock_priv *priv, u32 pll) argument 62 u32 ctrl = nv_rd32(priv, pll + 0x00); 63 u32 coef = nv_rd32(priv, pll + 0x04); 72 switch (pll) { 88 sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140); 392 { nvc0_clock_prog_2 }, /* (maybe) program pll */ 393 { nvc0_clock_prog_3 }, /* (maybe) select pll mode */
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H A D | nv04.c | 26 #include <subdev/bios/pll.h> 30 #include "pll.h"
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H A D | pllnva3.c | 27 #include <subdev/bios/pll.h> 29 #include "pll.h" 84 nv_error(subdev, "unable to find matching pll values\n");
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H A D | nv50.c | 26 #include <subdev/bios/pll.h> 29 #include "pll.h" 68 nv_error(priv, "ref: bad pll 0x%06x\n", base); 96 nv_error(priv, "ref: bad pll 0x%06x\n", base); 144 nv_error(priv, "bad pll 0x%06x\n", base); 322 struct nvbios_pll pll; local 325 ret = nvbios_pll_parse(bios, reg, &pll); 329 pll.vco2.max_freq = 0; 330 pll.refclk = read_pll_ref(priv, reg); 331 if (!pll [all...] |
H A D | nve0.c | 28 #include <subdev/bios/pll.h> 30 #include "pll.h" 59 read_pll(struct nve0_clock_priv *priv, u32 pll) argument 61 u32 ctrl = nv_rd32(priv, pll + 0x00); 62 u32 coef = nv_rd32(priv, pll + 0x04); 72 switch (pll) { 84 fN = nv_rd32(priv, pll + 0x10) >> 16; 90 sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140); 428 { 0x00ff, nve0_clock_prog_2 }, /* (maybe) program pll */ 430 { 0x007f, nve0_clock_prog_4_0 }, /* (maybe) select pll mod [all...] |
/drivers/video/fbdev/nvidia/ |
H A D | nv_hw.c | 144 unsigned int pll, N, M, MB, NB, P; local 147 pll = NV_RD32(par->PMC, 0x4020); 148 P = (pll >> 16) & 0x07; 149 pll = NV_RD32(par->PMC, 0x4024); 150 M = pll & 0xFF; 151 N = (pll >> 8) & 0xFF; 157 MB = (pll >> 16) & 0xFF; 158 NB = (pll >> 24) & 0xFF; 162 pll = NV_RD32(par->PMC, 0x4000); 163 P = (pll >> 1 684 unsigned int M, N, P, pll, MClk, NVClk, memctrl; local [all...] |
/drivers/video/fbdev/omap2/dss/ |
H A D | hdmi.h | 321 int hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp); 322 void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp); 323 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s); 324 void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy); 325 int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll);
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/drivers/clk/qcom/ |
H A D | Makefile | 5 clk-qcom-y += clk-pll.o
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/drivers/clk/samsung/ |
H A D | Makefile | 5 obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
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/drivers/media/dvb-frontends/ |
H A D | dib8000.h | 14 struct dibx000_bandwidth_config *pll; member in struct:dib8000_config 45 struct dibx000_bandwidth_config *pll, u32 bw, u8 ratio);
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H A D | dib8000.c | 691 const struct dibx000_bandwidth_config *pll = state->cfg.pll; local 696 (pll->pll_prediv << 8) | (pll->pll_ratio << 0)); 698 clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) | 699 (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) | 700 (1 << 3) | (pll->pll_range << 1) | 701 (pll->pll_reset << 0); 704 clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll 741 dib8000_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *pll, u32 bw, u8 ratio) argument [all...] |
/drivers/media/i2c/ |
H A D | smiapp-pll.h | 2 * drivers/media/i2c/smiapp-pll.h 112 struct smiapp_pll *pll);
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H A D | Makefile | 9 obj-$(CONFIG_VIDEO_APTINA_PLL) += aptina-pll.o 77 obj-$(CONFIG_VIDEO_SMIAPP_PLL) += smiapp-pll.o
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/drivers/clk/ |
H A D | clk-vt8500.c | 542 struct clk_pll *pll = to_clk_pll(hw); local 549 switch (pll->type) { 567 pr_err("%s: invalid pll type\n", __func__); 571 spin_lock_irqsave(pll->lock, flags); 574 writel(pll_val, pll->reg); 577 spin_unlock_irqrestore(pll->lock, flags); 585 struct clk_pll *pll = to_clk_pll(hw); local 589 switch (pll->type) { 616 struct clk_pll *pll = to_clk_pll(hw); local 617 u32 pll_val = readl(pll [all...] |
/drivers/gpu/drm/i915/ |
H A D | intel_ddi.c | 621 u32 val, pll; local 641 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; 642 if (pll == SPLL_PLL_FREQ_810MHz) 644 else if (pll == SPLL_PLL_FREQ_1350MHz) 646 else if (pll == SPLL_PLL_FREQ_2700MHz) 749 struct intel_shared_dpll *pll; local 761 pll = intel_get_shared_dpll(intel_crtc); 762 if (pll == NULL) { 768 intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); 1276 struct intel_shared_dpll *pll) 1275 hsw_ddi_pll_enable(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll) argument 1283 hsw_ddi_pll_disable(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll) argument 1293 hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) argument [all...] |
/drivers/video/fbdev/matrox/ |
H A D | matroxfb_DAC1064.c | 180 } else if (minfo->crtc2.pixclock == minfo->features.pll.ref_freq) { 588 minfo->features.pll.vco_freq_min = 62000; 589 minfo->features.pll.ref_freq = 14318; 590 minfo->features.pll.feed_div_min = 100; 591 minfo->features.pll.feed_div_max = 127; 592 minfo->features.pll.in_div_min = 1; 593 minfo->features.pll.in_div_max = 31; 594 minfo->features.pll.post_shift_max = 3; 726 matroxfb_g450_setclk(minfo, minfo->values.pll.video, M_VIDEO_PLL); 736 matroxfb_g450_setclk(minfo, minfo->values.pll [all...] |
/drivers/gpu/drm/nouveau/core/subdev/fb/ |
H A D | ramnva3.c | 27 #include <subdev/bios/pll.h> 32 #include <subdev/clock/pll.h> 153 if (mclk.pll) { 155 ram_wr32(fuc, 0x004004, mclk.pll); 193 if (!(ctrl & 0x00000008) && mclk.pll) { 198 ram_wr32(fuc, 0x004004, mclk.pll); 204 if (!mclk.pll) { 230 if (mclk.pll) { 298 if (mclk.pll) {
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/drivers/gpu/drm/radeon/ |
H A D | atombios_crtc.c | 447 * again can cause display problems if the pll is already 460 /* one other crtc is using this pll don't turn 564 /* reset the pll flags */ 636 /* adjust pll for deep color modes */ 1051 struct radeon_pll *pll; local 1062 pll = &rdev->clock.p1pll; 1065 pll = &rdev->clock.p2pll; 1070 pll = &rdev->clock.dcpll; 1074 /* update pll params */ 1075 pll 1834 int pll; local [all...] |
/drivers/video/fbdev/core/ |
H A D | svgalib.c | 381 int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node) argument 388 ar = pll->r_max; 398 while ((ar > pll->r_min) && (f_vco > pll->f_vco_max)) { 404 if ((f_vco < pll->f_vco_min) || (f_vco > pll->f_vco_max)) 412 am = pll->m_min; 413 an = pll->n_min; 415 while ((am <= pll->m_max) && (an <= pll [all...] |
/drivers/gpu/drm/msm/hdmi/ |
H A D | hdmi_phy_8960.c | 30 struct clk *pll; member in struct:hdmi_phy_8960 42 * To get the parent clock setup properly, we need to plug in hdmi pll 513 phy_8960->pll = devm_clk_register(hdmi->dev->dev, &phy_8960->pll_hw); 514 if (IS_ERR(phy_8960->pll)) { 515 ret = PTR_ERR(phy_8960->pll); 516 phy_8960->pll = NULL;
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