Searched refs:readl_relaxed (Results 26 - 50 of 161) sorted by relevance

1234567

/drivers/mmc/host/
H A Dsdhci-msm.c67 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
78 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
98 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
112 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
118 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
126 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
274 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
294 writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
298 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
302 writel_relaxed((readl_relaxed(hos
[all...]
H A Dmmci_qcom_dml.c65 config = readl_relaxed(base + DML_CONFIG);
77 config = readl_relaxed(base + DML_CONFIG);
85 config = readl_relaxed(base + DML_CONFIG);
90 config = readl_relaxed(base + DML_CONFIG);
H A Dsdhci-st.c35 ret = readl_relaxed(host->ioaddr + reg);
40 ret = readl_relaxed(host->ioaddr + reg);
/drivers/thermal/
H A Dspear_thermal.c49 *temp = (readl_relaxed(stdev->thermal_base) & 0x7F) * MD_FACTOR;
66 actual_mask = readl_relaxed(stdev->thermal_base);
90 actual_mask = readl_relaxed(stdev->thermal_base);
170 actual_mask = readl_relaxed(stdev->thermal_base);
/drivers/clocksource/
H A Dexynos_mct.c147 if (readl_relaxed(reg_base + stat_addr) & mask) {
160 reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
178 u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
182 lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
183 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
199 return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
253 tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
266 tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
355 tmp = readl_relaxed(reg_base + offset);
377 tmp = readl_relaxed(reg_bas
[all...]
H A Dcadence_ttc_timer.c121 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
150 readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
166 return (cycle_t)readl_relaxed(timer->base_addr +
172 return readl_relaxed(ttc_sched_clock_val_reg);
214 ctrl_reg = readl_relaxed(timer->base_addr +
221 ctrl_reg = readl_relaxed(timer->base_addr +
269 readl_relaxed(ttccs->ttc.base_addr +
498 clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
506 clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
H A Dqcom-timer.c53 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
64 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
73 while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
85 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
108 return readl_relaxed(source_base + TIMER_COUNT_VAL);
H A Dbcm2835_timer.c54 return readl_relaxed(system_clock);
77 writel_relaxed(readl_relaxed(system_clock) + event,
86 if (readl_relaxed(timer->control) & timer->match_mask) {
H A Darm_global_timer.c69 upper = readl_relaxed(gt_base + GT_COUNTER1);
72 lower = readl_relaxed(gt_base + GT_COUNTER0);
73 upper = readl_relaxed(gt_base + GT_COUNTER1);
143 if (!(readl_relaxed(gt_base + GT_INT_STATUS) &
/drivers/gpio/
H A Dgpio-omap.c109 l = readl_relaxed(reg);
145 l = readl_relaxed(reg);
158 return (readl_relaxed(reg) & (BIT(offset))) != 0;
165 return (readl_relaxed(reg) & (BIT(offset))) != 0;
170 int l = readl_relaxed(base + reg);
239 val = readl_relaxed(reg);
314 readl_relaxed(bank->base + bank->regs->leveldetect0);
316 readl_relaxed(bank->base + bank->regs->leveldetect1);
318 readl_relaxed(bank->base + bank->regs->risingdetect);
320 readl_relaxed(ban
[all...]
H A Dgpio-pxa.c191 gpdr = readl_relaxed(base + GPDR_OFFSET);
197 gafr = readl_relaxed(base + GAFR_OFFSET);
231 value = readl_relaxed(base + GPDR_OFFSET);
253 tmp = readl_relaxed(base + GPDR_OFFSET);
266 u32 gplr = readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET);
342 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
343 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
371 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
410 gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
441 grer = readl_relaxed(
[all...]
H A Dgpio-spear-spics.c70 tmp = readl_relaxed(spics->base + spics->perip_cfg);
102 tmp = readl_relaxed(spics->base + spics->perip_cfg);
118 tmp = readl_relaxed(spics->base + spics->perip_cfg);
/drivers/clk/mmp/
H A Dclk-apmu.c39 data = readl_relaxed(apmu->base) | apmu->enable_mask;
57 data = readl_relaxed(apmu->base) & ~apmu->enable_mask;
/drivers/irqchip/
H A Dirq-gic-common.c38 val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
48 if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
/drivers/media/rc/
H A Dir-hix5hd2.c23 #ifndef readl_relaxed
24 # define readl_relaxed readl macro
103 while (readl_relaxed(priv->base + IR_BUSY)) {
150 irq_sr = readl_relaxed(priv->base + IR_INTS);
158 symb_num = readl_relaxed(priv->base + IR_DATAH);
160 readl_relaxed(priv->base + IR_DATAL);
170 symb_num = readl_relaxed(priv->base + IR_DATAH);
172 symb_val = readl_relaxed(priv->base + IR_DATAL);
/drivers/mtd/nand/
H A Datmel_nand_nfc.h60 readl_relaxed((addr) + ATMEL_HSMC_NFC_##reg)
97 readl_relaxed((bitstatus) + nfc_base)
/drivers/video/fbdev/mmp/hw/
H A Dmmp_ctrl.c48 isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR);
49 imask = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA);
53 tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR);
56 } while ((isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR)) & imask);
136 tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
180 tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
191 tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
271 tmp = readl_relaxed(ctrl_regs(path) + intf_ctrl(path->id)) & 0x1;
279 tmp = readl_relaxed(ctrl_regs(path) + intf_rbswap_ctrl(path->id)) &
312 tmp = readl_relaxed(ctrl_reg
[all...]
/drivers/clk/hisilicon/
H A Dclk-hix5hd2.c177 val = readl_relaxed(clk->ctrl_reg);
183 val = readl_relaxed(clk->phy_reg);
206 val = readl_relaxed(clk->ctrl_reg);
221 val = readl_relaxed(clk->ctrl_reg);
226 val = readl_relaxed(clk->phy_reg);
239 val = readl_relaxed(clk->ctrl_reg);
244 val = readl_relaxed(clk->phy_reg);
/drivers/spi/
H A Dspi-qup.c151 u32 opstate = readl_relaxed(controller->base + QUP_STATE);
174 cur_state = readl_relaxed(controller->base + QUP_STATE);
213 state = readl_relaxed(controller->base + QUP_OPERATIONAL);
217 word = readl_relaxed(controller->base + QUP_INPUT_FIFO);
249 state = readl_relaxed(controller->base + QUP_OPERATIONAL);
282 qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS);
283 spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS);
284 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
386 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
395 config = readl_relaxed(controlle
[all...]
/drivers/clk/spear/
H A Dclk-vco-pll.c134 p = readl_relaxed(pll->vco->cfg_reg);
157 val = readl_relaxed(pll->vco->cfg_reg);
202 mode = (readl_relaxed(vco->mode_reg) >> PLL_MODE_SHIFT) & PLL_MODE_MASK;
204 val = readl_relaxed(vco->cfg_reg);
244 val = readl_relaxed(vco->mode_reg);
249 val = readl_relaxed(vco->cfg_reg);
/drivers/clk/berlin/
H A Dberlin2-pll.c67 val = readl_relaxed(pll->base + SPLL_CTRL0);
75 val = readl_relaxed(pll->base + SPLL_CTRL1);
/drivers/clk/mxs/
H A Dclk-frac.c46 div = readl_relaxed(frac->reg) >> frac->shift;
95 val = readl_relaxed(frac->reg);
/drivers/dma/
H A Dsa11x0-dma.c174 dcsr = readl_relaxed(base + DMA_DCSR_R);
259 dcsr = readl_relaxed(p->base + DMA_DCSR_R);
272 readl_relaxed(p->base + DMA_DDAR),
273 readl_relaxed(p->base + DMA_DBSA),
274 readl_relaxed(p->base + DMA_DBTA),
275 readl_relaxed(p->base + DMA_DBSB),
276 readl_relaxed(p->base + DMA_DBTB));
316 WARN_ON(readl_relaxed(p->base + DMA_DCSR_R) &
415 dcsr = readl_relaxed(p->base + DMA_DCSR_R);
423 return readl_relaxed(
[all...]
/drivers/i2c/busses/
H A Di2c-st.c201 writel_relaxed(readl_relaxed(reg) | mask, reg);
206 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
246 if (readl_relaxed(i2c_dev->base + SSC_STA) & SSC_STA_RIR)
249 count = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT) &
253 readl_relaxed(i2c_dev->base + SSC_RBUF);
345 sta = readl_relaxed(i2c_dev->base + SSC_STA);
382 sta = readl_relaxed(i2c_dev->base + SSC_STA);
386 tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT);
411 sta = readl_relaxed(i2c_dev->base + SSC_STA);
415 tx_fstat = readl_relaxed(i2c_de
[all...]
/drivers/phy/
H A Dphy-hix5hd2-sata.c85 val = readl_relaxed(priv->base + SATA_PHY0_CTLL);
94 val = readl_relaxed(priv->base + SATA_PORT_PHYCTL1);
101 val = readl_relaxed(priv->base + SATA_PORT_PHYCTL2);
109 val = readl_relaxed(priv->base + SATA_PORT_PHYCTL);

Completed in 706 milliseconds

1234567