Searched refs:reg_base (Results 51 - 75 of 155) sorted by relevance

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/drivers/usb/musb/
H A Dmusb_dsps.c218 void __iomem *reg_base = musb->ctrl_base; local
226 dsps_writel(reg_base, wrp->epintr_set, epmask);
227 dsps_writel(reg_base, wrp->coreintr_set, coremask);
229 dsps_writel(reg_base, wrp->coreintr_set,
243 void __iomem *reg_base = musb->ctrl_base; local
245 dsps_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap);
246 dsps_writel(reg_base, wrp->epintr_clear,
304 void __iomem *reg_base = musb->ctrl_base; local
315 epintr = dsps_readl(reg_base, wrp->epintr_status);
320 dsps_writel(reg_base, wr
444 void __iomem *reg_base; local
[all...]
/drivers/clk/samsung/
H A Dclk-s3c2410.c43 static void __iomem *reg_base; variable
64 samsung_clk_save(reg_base, s3c2410_save,
72 samsung_clk_restore(reg_base, s3c2410_save,
370 reg_base = base;
373 reg_base = of_iomap(np, 0);
374 if (!reg_base)
378 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
394 ARRAY_SIZE(s3c2410_plls), reg_base);
410 ARRAY_SIZE(s3c244x_common_plls), reg_base);
H A Dclk-exynos5410.c189 void __iomem *reg_base; local
191 reg_base = of_iomap(np, 0);
192 if (!reg_base)
195 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
198 ARRAY_SIZE(exynos5410_plls), reg_base);
H A Dclk-s3c64xx.c65 static void __iomem *reg_base; variable
100 samsung_clk_save(reg_base, s3c64xx_save_common,
104 samsung_clk_save(reg_base, s3c64xx_save_soc,
112 samsung_clk_restore(reg_base, s3c64xx_save_common,
116 samsung_clk_restore(reg_base, s3c64xx_save_soc,
465 reg_base = base;
469 reg_base = of_iomap(np, 0);
470 if (!reg_base)
474 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
484 ARRAY_SIZE(s3c64xx_pll_clks), reg_base);
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H A Dclk-s5pv210.c86 static void __iomem *reg_base; variable
139 samsung_clk_save(reg_base, s5pv210_clk_dump,
146 samsung_clk_restore(reg_base, s5pv210_clk_dump,
788 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
799 ARRAY_SIZE(s5p6442_pll_clks), reg_base);
810 ARRAY_SIZE(s5pv210_pll_clks), reg_base);
840 reg_base = of_iomap(np, 0);
841 if (!reg_base)
850 reg_base = of_iomap(np, 0);
851 if (!reg_base)
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H A Dclk-exynos4.c155 static void __iomem *reg_base; variable
299 pll_con = readl(reg_base + reg);
305 pll_con = readl(reg_base + reg);
311 samsung_clk_save(reg_base, exynos4_save_common,
313 samsung_clk_save(reg_base, exynos4_save_pll,
317 samsung_clk_save(reg_base, exynos4_save_soc,
319 samsung_clk_restore(reg_base, src_mask_suspend_e4210,
322 samsung_clk_save(reg_base, exynos4_save_soc,
326 samsung_clk_restore(reg_base, src_mask_suspend,
334 samsung_clk_restore(reg_base, exynos4_save_pl
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H A Dclk.c69 ctx->reg_base = base;
189 ctx->reg_base + list->offset,
222 ctx->reg_base + list->offset,
228 ctx->reg_base + list->offset, list->shift,
259 list->flags, ctx->reg_base + list->offset,
H A Dclk-exynos5250.c112 static void __iomem *reg_base; variable
177 samsung_clk_save(reg_base, exynos5250_save,
185 samsung_clk_restore(reg_base, exynos5250_save,
763 reg_base = of_iomap(np, 0);
764 if (!reg_base)
770 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
789 reg_base);
809 __raw_writel(tmp, reg_base + PWR_CTRL1);
819 __raw_writel(tmp, reg_base + PWR_CTRL2);
/drivers/spi/
H A Dspi-fsl-cpm.c75 struct fsl_spi_reg *reg_base = mspi->reg_base; local
95 mpc8xxx_spi_write_reg(&reg_base->command, SPCOM_STR);
102 struct fsl_spi_reg *reg_base = mspi->reg_base; local
147 mpc8xxx_spi_write_reg(&reg_base->mask, SPIE_RXB);
178 struct fsl_spi_reg *reg_base = mspi->reg_base; local
190 mpc8xxx_spi_write_reg(&reg_base->event, events);
/drivers/net/can/cc770/
H A Dcc770_platform.c69 return ioread8(priv->reg_base + reg);
75 iowrite8(val, priv->reg_base + reg);
202 priv->reg_base = base;
214 "reg_base=0x%p irq=%d clock=%d cpu_interface=0x%02x "
216 priv->reg_base, dev->irq, priv->can.clock.freq,
248 iounmap(priv->reg_base);
/drivers/power/
H A Dgoldfish_battery.c29 void __iomem *reg_base; member in struct:goldfish_battery_data
38 (readl(data->reg_base + addr))
40 (writel(x, data->reg_base + addr))
181 data->reg_base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
182 if (data->reg_base == NULL) {
/drivers/media/rc/img-ir/
H A Dimg-ir-core.c105 priv->reg_base = devm_ioremap_resource(&pdev->dev, res_regs);
106 if (IS_ERR(priv->reg_base))
107 return PTR_ERR(priv->reg_base);
/drivers/irqchip/
H A Dirq-zevio.c50 readl(gc->reg_base + regs->ack);
111 gc->reg_base = zevio_irq_io;
H A Dirq-sunxi-nmi.c53 irq_reg_writel(val, gc->reg_base + off);
58 return irq_reg_readl(gc->reg_base + off);
154 gc->reg_base = of_iomap(node, 0);
155 if (!gc->reg_base) {
/drivers/video/fbdev/mmp/hw/
H A Dmmp_ctrl.c48 isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR);
49 imask = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA);
53 tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR);
55 writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR);
56 } while ((isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR)) & imask);
335 tmp = readl_relaxed(ctrl->reg_base + LCD_TOP_CTRL);
337 writel_relaxed(tmp, ctrl->reg_base + LCD_TOP_CTRL);
343 tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA);
346 writel_relaxed(tmp, ctrl->reg_base + SPU_IRQ_ENA);
504 ctrl->reg_base
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/drivers/net/can/sja1000/
H A Dems_pcmcia.c81 return readb(priv->reg_base + port);
87 writeb(val, priv->reg_base + port);
218 priv->reg_base = card->base_addr + EMS_PCMCIA_CAN_BASE_OFFSET +
241 i, priv->reg_base, dev->irq);
H A Dkvaser_pci.c120 return ioread8(priv->reg_base + port);
126 iowrite8(val, priv->reg_base + port);
201 pci_iounmap(board->pci_dev, priv->reg_base);
253 priv->reg_base = base_addr + channel * KVASER_PCI_PORT_BYTES;
266 dev_info(&pdev->dev, "reg_base=%p conf_addr=%p irq=%d\n",
267 priv->reg_base, board->conf_addr, dev->irq);
H A Dplx_pci.c348 return ioread8(priv->reg_base + port);
353 iowrite8(val, priv->reg_base + port);
478 if (priv->reg_base)
479 pci_iounmap(pdev, priv->reg_base);
579 priv->reg_base = addr + cm->offset;
603 "registered as %s\n", i + 1, priv->reg_base,
/drivers/usb/host/
H A Dehci-pmcmsp.c49 struct ehci_regs *reg_base = ehci->regs; local
52 base = (u8 *)reg_base + USB_EHCI_REG_USB_MODE;
53 statreg = (u8 *)reg_base + USB_EHCI_REG_USB_STATUS;
54 fiforeg = (u8 *)reg_base + USB_EHCI_REG_USB_FIFO;
/drivers/mmc/host/
H A Dandroid-goldfish.c58 #define GOLDFISH_MMC_READ(host, addr) (readl(host->reg_base + addr))
59 #define GOLDFISH_MMC_WRITE(host, addr, x) (writel(x, host->reg_base + addr))
131 void __iomem *reg_base; member in struct:goldfish_mmc_host
479 host->reg_base = ioremap(res->start, resource_size(res));
480 if (host->reg_base == NULL) {
538 iounmap(host->reg_base);
554 iounmap(host->reg_base);
/drivers/pinctrl/samsung/
H A Dpinctrl-exynos5440.c106 * @reg_base: ioremapped based address of the register space.
114 void __iomem *reg_base; member in struct:exynos5440_pinctrl_priv_data
355 base = priv->reg_base;
408 base = priv->reg_base;
476 base = priv->reg_base;
555 void __iomem *base = priv->reg_base;
569 void __iomem *base = priv->reg_base;
582 void __iomem *base = priv->reg_base;
602 void __iomem *base = priv->reg_base;
887 gpio_int = readl(d->reg_base
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/drivers/net/can/mscan/
H A Dmscan.c64 struct mscan_regs __iomem *regs = priv->reg_base;
140 struct mscan_regs __iomem *regs = priv->reg_base;
180 struct mscan_regs __iomem *regs = priv->reg_base;
201 struct mscan_regs __iomem *regs = priv->reg_base;
309 struct mscan_regs __iomem *regs = priv->reg_base;
350 struct mscan_regs __iomem *regs = priv->reg_base;
413 struct mscan_regs __iomem *regs = priv->reg_base;
460 struct mscan_regs __iomem *regs = priv->reg_base;
540 struct mscan_regs __iomem *regs = priv->reg_base;
561 struct mscan_regs __iomem *regs = priv->reg_base;
[all...]
/drivers/gpio/
H A Dgpio-sta2x11.c53 void __iomem *reg_base; member in struct:gsta_gpio
329 chip->reg_base, handle_simple_irq);
377 chip->reg_base = devm_ioremap_resource(&dev->dev, res);
378 if (IS_ERR(chip->reg_base))
379 return PTR_ERR(chip->reg_base);
382 chip->regs[i] = chip->reg_base + i * 4096;
/drivers/pinctrl/
H A Dpinctrl-rockchip.c88 * @reg_base: register base of the gpio bank
106 void __iomem *reg_base; member in struct:rockchip_pin_bank
880 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
886 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1299 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1323 data = readl(bank->reg_base + GPIO_EXT_PORT);
1395 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1398 polarity = readl_relaxed(bank->reg_base +
1400 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1435 data = readl_relaxed(bank->reg_base
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/drivers/dma/ioat/
H A Ddma_v2.c62 writew(ioat->dmacount, chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
198 writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
316 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
361 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
362 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
380 dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
387 xfercap_log = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
532 writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
543 chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
545 chan->reg_base
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Completed in 548 milliseconds

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