Searched refs:val (Results 226 - 250 of 3672) sorted by relevance

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/drivers/crypto/ux500/cryp/
H A Dcryp_p.h26 #define CRYP_WRITE_BIT(reg_name, val, mask) \
28 ((val) & (mask))), reg_name)
30 #define CRYP_TEST_BITS(reg_name, val) \
31 (readl_relaxed(reg_name) & (val))
33 #define CRYP_PUT_BITS(reg, val, shift, mask) \
35 (((u32)val << shift) & (mask))), reg)
/drivers/iio/dac/
H A Dad5764.c125 unsigned int val)
131 st->data[0].d32 = cpu_to_be32((reg << 16) | val);
140 unsigned int *val)
161 *val = be32_to_cpu(st->data[1].d32) & 0xffff;
185 struct iio_chan_spec const *chan, int val, int val2, long info)
192 if (val >= max_val || val < 0)
194 val <<= chan->scan_type.shift;
197 if (val >= 128 || val <
124 ad5764_write(struct iio_dev *indio_dev, unsigned int reg, unsigned int val) argument
139 ad5764_read(struct iio_dev *indio_dev, unsigned int reg, unsigned int *val) argument
184 ad5764_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long info) argument
221 ad5764_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long info) argument
[all...]
/drivers/iio/gyro/
H A Dadis16260.c109 u16 val = ADIS16260_SLP_CNT_POWER_OFF; local
111 ret = adis_write_reg_16(adis, ADIS16260_SLP_CNT, val);
140 int *val, int *val2,
151 ADIS16260_ERROR_ACTIVE, val);
155 *val = 0;
165 *val = 0;
170 *val = 1;
173 *val = 0;
178 *val = 145;
185 *val
138 adis16260_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) argument
221 adis16260_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) argument
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/drivers/mfd/
H A Dwm831x-otp.c32 int i, val; local
35 val = wm831x_reg_read(wm831x, WM831X_UNIQUE_ID_1 + i);
36 if (val < 0)
37 return val;
39 id[i * 2] = (val >> 8) & 0xff;
40 id[(i * 2) + 1] = val & 0xff;
H A Dlm3533-ctrlbank.c79 u8 val; local
85 val = (imax - LM3533_MAX_CURRENT_MIN) / LM3533_MAX_CURRENT_STEP;
88 ret = lm3533_write(cb->lm3533, reg, val);
97 int lm3533_ctrlbank_set_##_name(struct lm3533_ctrlbank *cb, u8 val) \
102 if (val > LM3533_##_NAME##_MAX) \
106 ret = lm3533_write(cb->lm3533, reg, val); \
115 int lm3533_ctrlbank_get_##_name(struct lm3533_ctrlbank *cb, u8 *val) \
121 ret = lm3533_read(cb->lm3533, reg, val); \
/drivers/misc/
H A Dad525x_dpot-i2c.c15 static int write_d8(void *client, u8 val) argument
17 return i2c_smbus_write_byte(client, val);
20 static int write_r8d8(void *client, u8 reg, u8 val) argument
22 return i2c_smbus_write_byte_data(client, reg, val);
25 static int write_r8d16(void *client, u8 reg, u16 val) argument
27 return i2c_smbus_write_word_data(client, reg, val);
/drivers/net/dsa/
H A Dmv88e6xxx.h52 int reg, u16 val);
53 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val);
58 int mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum, u16 val);
62 int regnum, u16 val);
85 #define REG_WRITE(addr, reg, val) \
89 __ret = mv88e6xxx_reg_write(ds, addr, reg, val); \
/drivers/net/usb/
H A Dplusb.c70 pl_vendor_req(struct usbnet *dev, u8 req, u8 val, u8 index) argument
75 val, index, NULL, 0);
79 pl_clear_QuickLink_features(struct usbnet *dev, int val) argument
81 return pl_vendor_req(dev, 1, (u8) val, 0);
85 pl_set_QuickLink_features(struct usbnet *dev, int val) argument
87 return pl_vendor_req(dev, 3, (u8) val, 0);
/drivers/net/wireless/ath/ath6kl/
H A Dbmi.h226 #define ath6kl_bmi_write_hi32(ar, item, val) \
232 v = cpu_to_le32(val); \
236 #define ath6kl_bmi_read_hi32(ar, item, val) \
238 u32 addr, *check_type = val; \
242 (void) (check_type == val); \
246 *val = le32_to_cpu(tmp); \
/drivers/staging/comedi/drivers/
H A Drti802.c62 unsigned int val = data[i]; local
64 s->readback[chan] = val;
68 val = comedi_offset_munge(s, val);
70 outb(val & 0xff, dev->iobase + RTI802_DATALOW);
71 outb((val >> 8) & 0xff, dev->iobase + RTI802_DATAHIGH);
/drivers/usb/dwc2/
H A Dcore.h764 extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val);
776 extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val);
786 extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val);
796 extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val);
808 struct dwc2_hsotg *hsotg, int val);
820 int val);
829 int val);
836 extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val);
844 int val);
852 int val);
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/drivers/media/pci/pluto2/
H A Dpluto2.c144 static inline void pluto_writereg(struct pluto *pluto, u32 reg, u32 val) argument
146 writel(val, &pluto->io_mem[reg]);
151 u32 val = readl(&pluto->io_mem[reg]); local
152 val &= ~mask;
153 val |= bits;
154 writel(val, &pluto->io_mem[reg]);
157 static void pluto_write_tscr(struct pluto *pluto, u32 val) argument
160 val &= ~TSCR_ADEF;
161 val |= TS_DMA_PACKETS / 2;
163 pluto_writereg(pluto, REG_TSCR, val);
212 u32 val = pluto_readreg(pluto, REG_MISC); local
226 u32 val = pluto_readreg(pluto, REG_TSCR); local
373 u32 val = pluto_readreg(pluto, REG_TSCR); local
387 u32 val = pluto_readreg(pluto, REG_TSCR); local
541 u32 val = pluto_readreg(pluto, REG_MISC) & MISC_DVR; local
548 u32 val = pluto_readreg(pluto, REG_MMAC); local
576 u32 val = readl(&cis[i]); local
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/drivers/crypto/qat/qat_common/
H A Dicp_qat_fw.h52 #define QAT_FIELD_SET(flags, val, bitpos, mask) \
54 (((val) & (mask)) << (bitpos))) ; }
167 #define ICP_QAT_FW_COMN_OV_SRV_TYPE_SET(icp_qat_fw_comn_req_hdr_t, val) \
168 icp_qat_fw_comn_req_hdr_t.service_type = val
173 #define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_SET(icp_qat_fw_comn_req_hdr_t, val) \
174 icp_qat_fw_comn_req_hdr_t.service_cmd_id = val
179 #define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \
180 ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val)
190 #define ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) \
191 QAT_FIELD_SET((hdr_t.hdr_flags), (val), \
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/drivers/gpu/drm/nouveau/core/subdev/i2c/
H A Dnv04.c44 u8 val = nv_rdvgac(priv, 0, port->drive); local
45 if (state) val |= 0x20;
46 else val &= 0xdf;
47 nv_wrvgac(priv, 0, port->drive, val | 0x01);
55 u8 val = nv_rdvgac(priv, 0, port->drive); local
56 if (state) val |= 0x10;
57 else val &= 0xef;
58 nv_wrvgac(priv, 0, port->drive, val | 0x01);
/drivers/gpu/drm/nouveau/
H A Dnouveau_backlight.c44 int val = (nvif_rd32(device, NV40_PMC_BACKLIGHT) & local
47 return val;
55 int val = bd->props.brightness; local
59 (val << 16) | (reg & ~NV40_PMC_BACKLIGHT_MASK));
103 u32 val; local
105 val = nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(or));
106 val &= NV50_PDISP_SOR_PWM_CTL_VAL;
107 return ((val * 100) + (div / 2)) / div;
118 u32 val = (bd->props.brightness * div) / 100; local
121 NV50_PDISP_SOR_PWM_CTL_NEW | val);
138 u32 div, val; local
156 u32 div, val; local
[all...]
/drivers/gpu/drm/sti/
H A Dsti_mixer.c67 u32 reg_id, u32 val)
69 writel(val, mixer->regs + reg_id);
74 u32 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL); local
76 val &= ~GAM_CTL_BACK_MASK;
77 val |= enable;
78 sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
84 u32 val = (red << 16) | (green << 8) | blue; local
86 sti_mixer_reg_write(mixer, GAM_MIXER_BKC, val);
106 u32 mask, val; local
139 dev_dbg(mixer->dev, "GAM_MIXER_CRB val
66 sti_mixer_reg_write(struct sti_mixer *mixer, u32 reg_id, u32 val) argument
199 u32 mask, val; local
[all...]
/drivers/hwmon/
H A Dgl518sm.c84 #define RAW_FROM_REG(val) val
86 #define BOOL_FROM_REG(val) ((val) ? 0 : 1)
87 #define BOOL_TO_REG(val) ((val) ? 0 : 1)
89 #define TEMP_TO_REG(val) clamp_val(((((val) < 0 ? \
90 (val) - 500 : \
91 (val)
166 int val; local
359 unsigned long val; local
392 unsigned long val; local
[all...]
/drivers/ide/
H A Dsl82c105.c116 u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; local
118 pci_read_config_dword(dev, 0x40, &val);
120 return (val & mask) ? 1 : 0;
133 u16 val; local
135 pci_read_config_word(dev, 0x7e, &val);
136 pci_write_config_word(dev, 0x7e, val | (1 << 2));
137 pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
151 u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; local
159 pci_read_config_dword(dev, 0x40, &val);
160 if (val
224 u32 val; local
274 u32 val; local
[all...]
/drivers/isdn/hisax/
H A Dhisax_isac.c444 int val; local
446 val = cs->read_isac(cs, ISAC_RBCH);
447 DBG(1, "ISAC version (%x): %s", val, ISACVer[(val >> 5) & 3]);
515 unsigned char val; local
517 val = isac->read_isac(isac, ISAC_CIR0);
518 DBG(DBG_IRQ, "CIR0 %#x", val);
519 if (val & ISAC_CIR0_CIC0) {
520 DBG(DBG_IRQ, "CODR0 %#x", (val >> 2) & 0xf);
521 FsmEvent(&isac->l1m, (val >>
531 unsigned char val; local
584 unsigned char val; local
606 unsigned char val; local
645 unsigned char val; local
659 unsigned char val; local
714 unsigned char val; local
746 unsigned char val; local
774 int val, eval; local
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/drivers/media/dvb-frontends/
H A Dsi21xx.h28 static inline int si21xx_writeregister(struct dvb_frontend *fe, u8 reg, u8 val) argument
31 u8 buf[] = {reg, val};
/drivers/mtd/nand/
H A Dnuc900_nand.c48 #define write_data_reg(dev, val) \
49 __raw_writel((val), (dev)->reg + REG_SMDATA)
51 #define write_cmd_reg(dev, val) \
52 __raw_writel((val), (dev)->reg + REG_SMCMD)
54 #define write_addr_reg(dev, val) \
55 __raw_writel((val), (dev)->reg + REG_SMADDR)
116 unsigned int val; local
118 val = __raw_readl(REG_SMISR);
119 val &= READYBUSY;
122 return val;
221 unsigned int val; local
[all...]
/drivers/net/ethernet/qlogic/netxen/
H A Dnetxen_nic_hw.h88 #define netxen_gb_set_mii_mgmt_clockselect(config_word, val) \
89 ((config_word) |= ((val) & 0x07))
103 #define netxen_gb_mii_mgmt_reg_addr(config_word, val) \
104 ((config_word) |= ((val) & 0x1F))
105 #define netxen_gb_mii_mgmt_phy_addr(config_word, val) \
106 ((config_word) |= (((val) & 0x1F) << 8))
232 #define netxen_set_phy_speed(config_word, val) \
233 ((config_word) |= ((val & 0x03) << 14))
/drivers/pci/host/
H A Dpcie-designware.h60 void __iomem *dbi_base, u32 *val);
62 u32 val, void __iomem *dbi_base);
63 int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
64 int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
66 unsigned int devfn, int where, int size, u32 *val);
68 unsigned int devfn, int where, int size, u32 val);
79 int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
80 int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
/drivers/power/reset/
H A Dkeystone-reset.c74 u32 val; local
106 val = of_property_read_bool(np, "ti,soft-reset");
107 val = val ? RSCFG_RSTYPE_SOFT : RSCFG_RSTYPE_HARD;
113 ret = regmap_write(pllctrl_regs, rspll_offset + RSCFG_RG, val);
126 ret = of_property_read_u32_index(np, "ti,wdt-list", i, &val);
135 if (val >= WDT_MUX_NUMBER) {
141 rg = rsmux_offset + val * 4;
/drivers/staging/iio/trigger/
H A Diio-trig-bfin-timer.c86 unsigned int val; local
90 ret = kstrtouint(buf, 10, &val);
94 if (val > 100000)
102 if (val == 0)
105 val = get_sclk() / val;
106 if (val <= 4 || val <= st->duty)
109 set_gptimer_period(st->t->id, val);
110 set_gptimer_pwidth(st->t->id, val
125 unsigned long val; local
224 unsigned long long val; local
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