| /drivers/infiniband/hw/cxgb3/ |
| H A D | cxio_hal.h | 68 u32 wptr; member in struct:cxio_hal_ctrl_qp
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| H A D | iwch_provider.c | 263 if (cqe < Q_COUNT(chp->cq.rptr, chp->cq.wptr)) {
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| /drivers/scsi/qla2xxx/ |
| H A D | qla_isr.c | 266 uint16_t __iomem *wptr; local
281 wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1);
285 wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8);
287 ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr);
289 ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
291 wptr++;
304 uint16_t __iomem *wptr; local
309 wptr = (uint16_t __iomem *)®24->mailbox1;
311 wptr = (uint16_t __iomem *)®82->mailbox_out[1];
315 for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr
2452 uint16_t __iomem *wptr; local
[all...] |
| H A D | qla_mr.c | 2869 uint32_t __iomem *wptr; local
2879 wptr = (uint32_t __iomem *)®->mailbox17;
2882 ha->mailbox_out32[cnt] = RD_REG_DWORD(wptr);
2883 wptr++;
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| H A D | qla_nx.c | 1986 uint16_t __iomem *wptr; local
1989 wptr = (uint16_t __iomem *)®->mailbox_out[1];
1996 ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
1997 wptr++;
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| /drivers/scsi/qla4xxx/ |
| H A D | ql4_nx.c | 3721 uint16_t *wptr; local
3729 wptr = (uint16_t *)ha->request_ring;
3744 if (*wptr == __constant_cpu_to_le16(0xffff))
3756 chksum += le16_to_cpu(*wptr++);
3835 uint16_t *wptr; local
3844 wptr = (uint16_t *)ha->request_ring;
3849 if (*wptr == __constant_cpu_to_le16(0xffff))
3858 chksum += le16_to_cpu(*wptr++);
3898 uint32_t *wptr; local
3902 wptr
[all...] |
| /drivers/gpu/drm/radeon/ |
| H A D | si.c | 3379 next_rptr = ring->wptr + 3 + 4 + 8;
3385 next_rptr = ring->wptr + 5 + 4 + 8;
3639 ring->wptr = 0;
3640 WREG32(CP_RB0_WPTR, ring->wptr);
3670 ring->wptr = 0;
3671 WREG32(CP_RB1_WPTR, ring->wptr);
3694 ring->wptr = 0;
3695 WREG32(CP_RB2_WPTR, ring->wptr);
5885 /* set rptr, wptr to 0 */
5999 /* set rptr, wptr t
6320 u32 wptr, tmp; local
6355 u32 wptr; local
[all...] |
| H A D | cik.c | 4060 next_rptr = ring->wptr + 3 + 4;
4066 next_rptr = ring->wptr + 5 + 4;
4402 ring->wptr = 0;
4403 WREG32(CP_RB0_WPTR, ring->wptr);
4453 u32 wptr; local
4455 wptr = RREG32(CP_RB0_WPTR);
4457 return wptr;
4463 WREG32(CP_RB0_WPTR, ring->wptr);
4488 u32 wptr; local
4492 wptr
7744 u32 wptr, tmp; local
7803 u32 wptr; local
[all...] |
| H A D | evergreen.c | 2800 next_rptr = ring->wptr + 3 + 4;
2806 next_rptr = ring->wptr + 5 + 4;
2958 ring->wptr = 0;
2959 WREG32(CP_RB_WPTR, ring->wptr);
4745 u32 wptr, tmp; local
4748 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
4750 wptr = RREG32(IH_RB_WPTR);
4752 if (wptr & RB_OVERFLOW) {
4753 wptr &= ~RB_OVERFLOW;
4755 * from the last not overwritten vector (wptr
4770 u32 wptr; local
[all...] |
| H A D | r100.c | 1062 u32 wptr; local
1064 wptr = RREG32(RADEON_CP_RB_WPTR);
1066 return wptr;
1072 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1172 ring->wptr = 0;
1173 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
2986 seq_printf(m, "Ring wptr %u\n", r_wptr);
2988 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2990 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
3671 u32 next_rptr = ring->wptr
[all...] |
| H A D | radeon.h | 827 unsigned wptr; member in struct:radeon_ring
2804 ring->ring[ring->wptr++] = v;
2805 ring->wptr &= ring->ptr_mask;
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| /drivers/net/ethernet/micrel/ |
| H A D | ks8851_mll.c | 544 * @wptr: buffer address to save data
548 static inline void ks_inblk(struct ks_net *ks, u16 *wptr, u32 len) argument
552 *wptr++ = (u16)ioread16(ks->hw_addr);
558 * @wptr: buffer address
562 static inline void ks_outblk(struct ks_net *ks, u16 *wptr, u32 len) argument
566 iowrite16(*wptr++, ks->hw_addr);
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| /drivers/net/ethernet/sun/ |
| H A D | cassini.c | 4163 u32 wptr, rptr; local
4175 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR);
4177 if ((val == 0) && (wptr != rptr)) {
4180 val, wptr, rptr);
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