Searched refs:writel (Results 276 - 300 of 1027) sorted by relevance

<<11121314151617181920>>

/drivers/mtd/nand/
H A Dlpc32xx_slc.c227 writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base));
231 writel(0, SLC_CFG(host->io_base));
232 writel(0, SLC_IEN(host->io_base));
233 writel((SLCSTAT_INT_TC | SLCSTAT_INT_RDY_EN),
250 writel(tmp, SLC_TAC(host->io_base));
269 writel(tmp, SLC_CFG(host->io_base));
273 writel(cmd, SLC_CMD(host->io_base));
275 writel(cmd, SLC_ADDR(host->io_base));
368 writel((uint32_t)*buf++, SLC_DATA(host->io_base));
509 writel(read
[all...]
H A Djz4740_nand.c98 writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
125 writel(reg, nand->base + JZ_REG_NAND_CTRL);
142 writel(0, nand->base + JZ_REG_NAND_IRQ_STAT);
162 writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
187 writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
250 writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
261 writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
362 writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
398 writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
535 writel(
[all...]
/drivers/power/reset/
H A Dat91-poweroff.c71 writel(AT91_SHDW_KEY | AT91_SHDW_SHDW, at91_shdwc_base + AT91_SHDW_CR);
118 writel(wakeup_mode | mode, at91_shdwc_base + AT91_SHDW_MR);
/drivers/reset/
H A Dreset-socfpga.c49 writel(reg | BIT(offset), data->membase + OFFSET_MODRST +
71 writel(reg & ~BIT(offset), data->membase + OFFSET_MODRST +
/drivers/scsi/
H A D3w-9xxx.h455 #define TW_CLEAR_ALL_INTERRUPTS(x) (writel(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
456 #define TW_CLEAR_ATTENTION_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
457 #define TW_CLEAR_HOST_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
458 #define TW_DISABLE_INTERRUPTS(x) (writel(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
459 #define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
460 #define TW_MASK_COMMAND_INTERRUPT(x) (writel(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
461 #define TW_UNMASK_COMMAND_INTERRUPT(x) (writel(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
462 #define TW_SOFT_RESET(x) (writel(TW_CONTROL_ISSUE_SOFT_RESET | \
/drivers/soc/tegra/fuse/
H A Dfuse-tegra.c92 writel(reg, base + 0x48);
100 writel(reg, base + 0x14);
/drivers/net/ethernet/natsemi/
H A Dnatsemi.c710 writel(1, ns_ioaddr(dev) + IntrEnable);
716 writel(0, ns_ioaddr(dev) + IntrEnable);
1007 writel(EE_Write0, ee_addr);
1012 writel(dataval, ee_addr);
1014 writel(dataval | EE_ShiftClk, ee_addr);
1017 writel(EE_ChipSelect, ee_addr);
1021 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
1024 writel(EE_ChipSelect, ee_addr);
1029 writel(EE_Write0, ee_addr);
1030 writel(
[all...]
/drivers/mmc/host/
H A Ds3cmci.c269 writel(newmask, host->base + host->sdiimsk);
281 writel(newmask, host->base + host->sdiimsk);
292 writel(mask, host->base + host->sdiimsk);
429 writel(host->prescaler, host->base + S3C2410_SDIPRE);
545 writel(*ptr++, to_ptr);
623 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
784 writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
785 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
873 writel(host->prescaler, host->base + S3C2410_SDIPRE);
884 writel(
[all...]
H A Dpxamci.c142 writel(STOP_CLOCK, host->base + MMC_STRPCL);
162 writel(host->imask, host->base + MMC_I_MASK);
172 writel(host->imask, host->base + MMC_I_MASK);
190 writel(nob, host->base + MMC_NOB);
191 writel(data->blksz, host->base + MMC_BLKLEN);
196 writel((timeout + 255) / 256, host->base + MMC_RDTO);
280 writel(cmd->opcode, host->base + MMC_CMD);
281 writel(cmd->arg >> 16, host->base + MMC_ARGH);
282 writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
283 writel(cmda
[all...]
/drivers/tty/serial/
H A Dioc3_serial.c389 writel(SSCR_RESET, &port->ip_serial_regs->sscr);
407 writel(0, &port->ip_serial_regs->sscr);
413 writel(port->ip_tx_prod, &port->ip_serial_regs->stpir);
415 writel(port->ip_rx_cons | SRCIR_ARM, &port->ip_serial_regs->srcir);
439 writel(0, &port->ip_serial_regs->shadow);
452 writel((unsigned int)((uint64_t) ring_pci_addr >> 32), sbbr_h);
453 writel((unsigned int)ring_pci_addr | BUF_SIZE_BIT, sbbr_l);
457 writel(SRTR_HZ / 100, &port->ip_serial_regs->srtr);
470 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
504 writel(por
[all...]
H A Dioc4_serial.c675 writel(val, &mem->sio_ies.raw);
679 writel(val, &mem->sio_iec.raw);
687 writel(val, &mem->other_ies.raw);
691 writel(val, &mem->other_iec.raw);
834 writel(IOC4_SSCR_RESET, &port->ip_serial_regs->sscr);
842 writel(0, &port->ip_serial_regs->sscr);
848 writel(port->ip_tx_prod, &port->ip_serial_regs->stpir);
850 writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir);
895 writel((unsigned int)((uint64_t)ring_pci_addr >> 32), sbbr_h);
896 writel((unsigne
[all...]
/drivers/thermal/samsung/
H A Dexynos_tmu.c139 writel(val_irq, data->base + reg->tmu_intclear);
170 writel(ctrl, data->base +
243 writel(rising_threshold,
245 writel(falling_threshold,
260 writel(rising_threshold,
266 writel(rising_threshold,
271 writel(con, data->base + reg->tmu_ctrl);
276 writel(0, data->base_second + reg->tmu_pmin);
327 writel(interrupt_en, data->base + reg->tmu_inten);
328 writel(co
[all...]
/drivers/gpu/drm/exynos/
H A Dexynos_drm_dsi.c353 writel(DSIM_SWRST, dsi->reg_base + DSIM_SWRST_REG);
440 writel(500, dsi->reg_base + driver_data->plltmr_reg);
462 writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);
510 writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
525 writel(reg, dsi->reg_base + DSIM_PHYCTRL_REG);
533 writel(reg, dsi->reg_base + DSIM_PHYTIMING_REG);
552 writel(reg, dsi->reg_base + DSIM_PHYTIMING1_REG);
565 writel(reg, dsi->reg_base + DSIM_PHYTIMING2_REG);
575 writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
579 writel(re
[all...]
/drivers/net/ethernet/chelsio/cxgb/
H A Dsge.c484 writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL);
498 writel(val, adapter->regs + A_SG_DOORBELL);
723 writel((u32)addr, adapter->regs + base_reg_lo);
724 writel(addr >> 32, adapter->regs + base_reg_hi);
725 writel(size, adapter->regs + size_reg);
740 writel(sge->sge_control, adapter->regs + A_SG_CONTROL);
753 writel(0, ap->regs + A_SG_CONTROL);
766 writel(SGE_RX_SM_BUF_SIZE + 1, ap->regs + A_SG_FLTHRESHOLD);
770 writel((u32)sge->respQ.size - 1, ap->regs + A_SG_RSPQUEUECREDIT);
889 writel(irqholdoff_re
[all...]
/drivers/ata/
H A Dsata_promise.c370 writel(tmp, sata_mmio + PDC_PHYMODE4);
417 writel(0, sata_mmio + PDC_INTERNAL_DEBUG_1);
429 writel(0xffffffff, sata_mmio + PDC_SATA_ERROR);
430 writel(0xffff0000, sata_mmio + PDC_LINK_LAYER_ERRORS);
444 writel(tmp, ata_ctlstat_mmio);
454 writel(tmp, ata_ctlstat_mmio);
458 writel(tmp, ata_ctlstat_mmio);
497 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
724 writel(tmp, ata_mmio + PDC_CTLSTAT);
745 writel(hotplug_statu
[all...]
/drivers/net/ethernet/freescale/
H A Dfec_main.c564 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
769 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
869 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i));
881 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i));
885 writel(RCMR_MATCHEN | RCMR_CMP(i),
891 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i));
895 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
939 writel(0, fep->hwp + FEC_ECNTRL);
941 writel(1, fep->hwp + FEC_ECNTRL);
951 writel(cpu_to_be3
[all...]
/drivers/clk/mxs/
H A Dclk-ssp.c54 writel(val, ssp->base + HW_SSP_TIMING(ssp));
/drivers/clk/rockchip/
H A Dclk-cpu.c118 writel(clksel->val , cpuclk->reg_base + clksel->reg);
157 writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask,
163 writel(HIWORD_UPDATE(1, 1, reg_data->mux_core_shift),
196 writel(HIWORD_UPDATE(0, reg_data->div_core_mask,
/drivers/cpuidle/
H A Dcpuidle-kirkwood.c36 writel(0x7, ddr_operation_base);
/drivers/gpio/
H A Dgpio-sodaville.c76 writel(reg, type_reg);
143 writel(0, sd->gpio_pub_base + GPIO_INT);
144 writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);
226 writel(mux_val, sd->gpio_pub_base + GPMUXCTL);
/drivers/i2c/busses/
H A Di2c-s3c2410.c201 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
209 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
219 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
227 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
275 writel(stat, i2c->regs + S3C2410_IICSTAT);
286 writel(iiccon, i2c->regs + S3C2410_IICCON);
289 writel(stat, i2c->regs + S3C2410_IICSTAT);
349 writel(iicstat, i2c->regs + S3C2410_IICSTAT);
559 writel(tmp, i2c->regs + S3C2410_IICCON);
587 writel(tm
[all...]
/drivers/input/keyboard/
H A Dst-keyscan.c70 writel(keypad->debounce_us * (clk_get_rate(keypad->clk) / 1000000),
73 writel(((keypad->n_cols - 1) << KEYSCAN_MATRIX_DIM_X_SHIFT) |
77 writel(KEYSCAN_CONFIG_ENABLE, keypad->base + KEYSCAN_CONFIG_OFF);
84 writel(0, keypad->base + KEYSCAN_CONFIG_OFF);
/drivers/memory/
H A Dtegra30-mc.c112 writel(val, mc->regs[0] + offs);
114 writel(val, mc->regs[1] + offs - 0x3c);
116 writel(val, mc->regs[2] + offs - 0x200);
118 writel(val, mc->regs[3] + offs - 0x284);
/drivers/misc/ibmasm/
H A Dremote.h97 #define clear_mouse_interrupt(sp) writel(0, mouse_addr(sp) + CONDOR_MOUSE_ISR_STATUS)
98 #define enable_mouse_interrupts(sp) writel(1, mouse_addr(sp) + CONDOR_MOUSE_ISR_CONTROL)
99 #define disable_mouse_interrupts(sp) writel(0, mouse_addr(sp) + CONDOR_MOUSE_ISR_CONTROL)
106 #define set_queue_reader(sp, reader) writel(reader, mouse_addr(sp) + CONDOR_MOUSE_Q_READER)
/drivers/net/ethernet/intel/i40evf/
H A Di40e_osdep.h45 #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg)))

Completed in 719 milliseconds

<<11121314151617181920>>