Searched refs:writel (Results 51 - 75 of 1027) sorted by relevance

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/drivers/thermal/
H A Darmada_thermal.c84 writel(reg, priv->control);
89 writel(reg, priv->control);
93 writel((reg | PMU_TDC0_SW_RST_MASK), priv->control);
95 writel(reg, priv->control);
100 writel(reg, priv->sensor);
110 writel(reg, priv->control);
115 writel(reg, priv->control);
118 writel(reg, priv->control);
133 writel(A375_Z1_CAL_RESET_LSB, priv->control);
134 writel(A375_Z1_CAL_RESET_MS
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/drivers/i2c/busses/
H A Di2c-sirf.c115 writel(regval,
128 writel(regval,
130 writel(siic->buf[siic->finished_len++],
137 writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START);
148 writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS);
160 writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET,
175 writel(SIRFSOC_I2C_STAT_CMD_DONE, siic->base + SIRFSOC_I2C_STATUS);
191 writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
201 writel(addr, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
212 writel(regva
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/drivers/irqchip/
H A Dirq-vic.c106 writel(VIC_VECT_CNTL_ENABLE | i, reg);
109 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
122 writel(vic->int_select, base + VIC_INT_SELECT);
123 writel(vic->protect, base + VIC_PROTECT);
126 writel(vic->int_enable, base + VIC_INT_ENABLE);
127 writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
131 writel(vic->soft_int, base + VIC_INT_SOFT);
132 writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
157 writel(vic->resume_irqs, base + VIC_INT_ENABLE);
158 writel(~vi
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/drivers/memstick/host/
H A Dtifm_ms.c142 writel(TIFM_MS_SYS_FDIR | readl(sock->addr + SOCK_MS_SYSTEM),
144 writel(host->io_word, sock->addr + SOCK_MS_DATA);
157 writel(TIFM_MS_SYS_FDIR | readl(sock->addr + SOCK_MS_SYSTEM),
238 writel(TIFM_MS_SYS_FDIR
241 writel(host->io_word, sock->addr + SOCK_MS_DATA);
243 writel(TIFM_MS_SYS_FDIR
246 writel(0, sock->addr + SOCK_MS_DATA);
279 writel(TIFM_FIFO_INT_SETALL,
281 writel(TIFM_FIFO_ENABLE,
294 writel(ilog
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/drivers/media/platform/exynos4-is/
H A Dfimc-reg.c28 writel(cfg, dev->regs + FIMC_REG_CISRCFMT);
33 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
38 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
97 writel(cfg, dev->regs + FIMC_REG_CITRGFMT);
103 writel(flip, dev->regs + FIMC_REG_MSCTRL);
142 writel(cfg, dev->regs + FIMC_REG_CITRGFMT);
147 writel(cfg, dev->regs + FIMC_REG_CITAREA);
157 writel(cfg, dev->regs + FIMC_REG_ORGOSIZE);
165 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
179 writel(cf
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/drivers/clocksource/
H A Dsun4i_timer.c62 writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
68 writel(delay, timer_base + TIMER_INTVAL_REG(timer));
80 writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
128 writel(0x1, timer_base + TIMER_IRQ_ST_REG);
168 writel(~0, timer_base + TIMER_INTVAL_REG(1));
169 writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
179 writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
197 writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
H A Dmtk_timer.c73 writel(val & ~TIMER_CTRL_ENABLE, evt->gpt_base +
80 writel(delay, evt->gpt_base + TIMER_CMP_REG(timer));
89 writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG);
101 writel(val | TIMER_CTRL_ENABLE | TIMER_CTRL_CLEAR,
145 writel(GPT_IRQ_ACK(GPT_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG);
154 writel(0x0, evt->gpt_base + GPT_IRQ_EN_REG);
156 writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG);
162 writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE,
165 writel(TIMER_CLK_SRC(TIMER_CLK_SRC_SYS13M) | TIMER_CLK_DIV1,
168 writel(
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H A Dtime-orion.c56 writel(delta, timer_base + TIMER1_VAL);
68 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD);
69 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL);
122 writel(~0, timer_base + TIMER0_VAL);
123 writel(~0, timer_base + TIMER0_RELOAD);
H A Dtimer-sun5i.c60 writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
67 writel(delay, timer_base + TIMER_INTVAL_LO_REG(timer));
79 writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
127 writel(0x1, timer_base + TIMER_IRQ_ST_REG);
171 writel(~0, timer_base + TIMER_INTVAL_LO_REG(1));
172 writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
187 writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
/drivers/net/ethernet/intel/ixgb/
H A Dixgb_osdep.h49 writel((value), ((a)->hw_addr + IXGB_##reg)))
55 writel((value), ((a)->hw_addr + IXGB_##reg + ((offset) << 2))))
/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac100_core.c40 writel((value | MAC_CORE_INIT), ioaddr + MAC_CONTROL);
43 writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
112 writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
113 writel(0xffffffff, ioaddr + MAC_HASH_LOW);
140 writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
141 writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
144 writel(value, ioaddr + MAC_CONTROL);
155 writel(flow, ioaddr + MAC_FLOW_CTRL);
H A Ddwmac1000_core.c45 writel(value, ioaddr + GMAC_CONTROL);
48 writel(0x207, ioaddr + GMAC_INT_MASK);
52 writel(0x0, ioaddr + GMAC_VLAN_TAG);
66 writel(value, ioaddr + GMAC_CONTROL);
111 writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);
112 writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);
127 writel(mcfilterbits[regs],
196 writel(value, ioaddr + GMAC_FRAME_FILTER);
221 writel(flow, ioaddr + GMAC_FLOW_CTRL);
238 writel(pm
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/drivers/scsi/pm8001/
H A Dpm8001_chips.h63 writel(val, pm8001_ha->io_mem[bar].memvirtaddr + addr);
71 writel(val, addr + offset);
/drivers/watchdog/
H A Dpnx4008_wdt.c90 writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
95 writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base));
97 writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
99 writel(MATCH_INT, WDTIM_INT(wdt_base));
101 writel(0xFFFF, WDTIM_PULSE(wdt_base));
102 writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
104 writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base));
114 writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */
/drivers/misc/ibmasm/
H A Dlowlevel.h68 writel( readl(ctrl_reg) & ~mask, ctrl_reg);
74 writel( readl(ctrl_reg) | mask, ctrl_reg);
114 writel(mfa, base_address + OUTBOUND_QUEUE_PORT);
129 writel(mfa, base_address + INBOUND_QUEUE_PORT);
/drivers/scsi/qla4xxx/
H A Dql4_inline.h42 writel(set_rmask(IMR_SCSI_INTR_ENABLE),
46 writel(set_rmask(CSR_SCSI_INTR_ENABLE), &ha->reg->ctrl_status);
56 writel(clr_rmask(IMR_SCSI_INTR_ENABLE),
60 writel(clr_rmask(CSR_SCSI_INTR_ENABLE), &ha->reg->ctrl_status);
/drivers/usb/phy/
H A Dphy-tegra-usb.c215 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
220 writel(val, base + TEGRA_USB_PORTSC1);
235 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
242 writel(val, base + TEGRA_USB_PORTSC1);
280 writel(val, base + UTMIP_BIAS_CFG0);
305 writel(val, base + UTMIP_BIAS_CFG0);
335 writel(val, base + USB_SUSP_CTRL);
341 writel(val, base + USB_SUSP_CTRL);
357 writel(val, base + USB_SUSP_CTRL);
363 writel(va
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/drivers/pci/host/
H A Dpci-xgene.c80 writel(val, addr + offset);
98 writel(val32, addr + (offset & ~0x3));
124 writel(val32, addr + (offset & ~0x3));
194 writel(rtdid_val, port->csr_base + RTDID);
290 writel(val, csr_base + addr);
294 writel(val, csr_base + addr + 0x04);
298 writel(val, csr_base + addr + 0x04);
302 writel(val, csr_base + addr + 0x08);
385 writel(lower_32_bits(cpu_addr), base);
386 writel(upper_32_bit
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H A Dpci-keystone-dw.c117 writel(BIT(bit_pos),
119 writel(reg_offset + MSI_IRQ_OFFSET, ks_pcie->va_app_base + IRQ_EOI);
128 writel(BIT(bit_pos),
138 writel(BIT(bit_pos),
233 writel(0x1, ks_pcie->va_app_base + IRQ_ENABLE_SET + (i << 4));
252 writel(offset, ks_pcie->va_app_base + IRQ_EOI);
301 writel(DBI_CS2_EN_VAL | readl(reg_virt + CMD_STATUS),
319 writel(~DBI_CS2_EN_VAL & readl(reg_virt + CMD_STATUS),
335 writel(0, pp->dbi_base + PCI_BASE_ADDRESS_0);
336 writel(
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/drivers/mtd/spi-nor/
H A Dfsl-quadspi.c253 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
254 writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
259 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
260 writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
270 writel(reg, q->iobase + QUADSPI_FR);
291 writel(0, base + QUADSPI_LUT_BASE + i * 4);
307 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
309 writel(LUT0(DUMMY, PAD1, dummy) | LUT1(READ, PAD4, rxfifo),
314 writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
328 writel(LUT
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/drivers/phy/
H A Dphy-exynos5250-usb2.c233 writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
239 writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
262 writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
266 writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
285 writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
295 writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL1);
296 writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL2);
299 writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL1);
300 writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL2);
311 writel(ehc
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/drivers/usb/gadget/udc/
H A Dnet2280.h30 writel(index, &regs->idxaddr);
38 writel(index, &regs->idxaddr);
39 writel(value, &regs->idxdata);
122 writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) |
136 writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE), &ep->regs->ep_rsp);
199 writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) |
209 writel(BIT(CLEAR_ENDPOINT_HALT) |
261 writel(BIT(GPIO3_LED_SELECT) |
290 writel(val, &dev->regs->gpioctl);
303 writel(va
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/drivers/net/ethernet/moxa/
H A Dmoxart_ether.c36 writel(value, priv->base + reg);
88 writel(SW_RST, priv->base + REG_MAC_CTRL);
92 writel(0, priv->base + REG_INTERRUPT_MASK);
101 writel(0x00001010, priv->base + REG_INT_TIMER_CTRL);
102 writel(0x00000001, priv->base + REG_APOLL_TIMER_CTRL);
103 writel(0x00000390, priv->base + REG_DMA_BLEN_CTRL);
106 writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
109 writel(priv->reg_maccr, priv->base + REG_MAC_CTRL);
124 writel(TX_DESC1_END, desc + TX_REG_OFFSET_DESC1);
132 writel(RX_DESC0_DMA_OW
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/drivers/staging/comedi/drivers/
H A Drtd520.c494 writel(0, dev->mmio + LAS0_CGT_CLEAR);
495 writel(1, dev->mmio + LAS0_CGT_ENABLE);
497 writel(rtd_convert_chan_gain(dev, list[ii], ii),
501 writel(0, dev->mmio + LAS0_CGT_ENABLE);
502 writel(rtd_convert_chan_gain(dev, list[0], 0),
516 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
519 writel(0, dev->mmio + LAS0_ADC_CONVERSION);
536 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
568 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
574 writel(
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/drivers/video/fbdev/
H A Dfb-puv3.c164 writel(((u32 *)(info->pseudo_palette))[fg_color], UGE_FCOLOR);
165 writel(0, UGE_BCOLOR);
166 writel(src_pitch, UGE_PITCH);
167 writel(src_offset, UGE_SRCSTART);
168 writel(dst_offset, UGE_DSTSTART);
169 writel(awidth, UGE_WIDHEIGHT);
170 writel(top, UGE_CLIP0);
171 writel(bottom, UGE_CLIP1);
172 writel(alpha_r, UGE_ROPALPHA);
173 writel(src_x
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Completed in 522 milliseconds

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