/drivers/net/phy/ |
H A D | mdio-sun4i.c | 46 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); 48 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); 59 writel(0x0, data->membase + EMAC_MAC_MCMD_REG); 73 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); 75 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); 86 writel(0x0, data->membase + EMAC_MAC_MCMD_REG); 88 writel(value, data->membase + EMAC_MAC_MWTD_REG);
|
/drivers/watchdog/ |
H A D | moxart_wdt.c | 43 writel(1, moxart_wdt->base + REG_COUNT); 44 writel(0x5ab9, moxart_wdt->base + REG_MODE); 45 writel(0x03, moxart_wdt->base + REG_ENABLE); 54 writel(0, moxart_wdt->base + REG_ENABLE); 63 writel(moxart_wdt->clock_frequency * wdt_dev->timeout, 65 writel(0x5ab9, moxart_wdt->base + REG_MODE); 66 writel(0x03, moxart_wdt->base + REG_ENABLE);
|
H A D | qcom-wdt.c | 45 writel(0, wdt->base + WDT_EN); 46 writel(1, wdt->base + WDT_RST); 47 writel(wdd->timeout * wdt->rate, wdt->base + WDT_BITE_TIME); 48 writel(1, wdt->base + WDT_EN); 56 writel(0, wdt->base + WDT_EN); 64 writel(1, wdt->base + WDT_RST); 102 writel(0, wdt->base + WDT_EN); 103 writel(1, wdt->base + WDT_RST); 104 writel(timeout, wdt->base + WDT_BITE_TIME); 105 writel( [all...] |
/drivers/ata/ |
H A D | ahci_tegra.c | 182 writel(val, tegra->sata_regs + SATA_CONFIGURATION_0); 195 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); 205 writel(val, tegra->sata_regs + SCFG_OFFSET + 216 writel(val, tegra->sata_regs + SCFG_OFFSET + 219 writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ, 221 writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1, 224 writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); 230 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA); 232 writel(0x01060100, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC); 236 writel(va [all...] |
/drivers/misc/ |
H A D | arm-charlcd.c | 82 writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); 98 writel(0x00, lcd->virtbase + CHAR_MASK); 132 writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); 150 writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); 166 writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); 168 writel(0x01, lcd->virtbase + CHAR_MASK); 190 writel(cmdhi, lcd->virtbase + CHAR_COM); 192 writel(cmdlo, lcd->virtbase + CHAR_COM); 201 writel(chhi, lcd->virtbase + CHAR_DAT); 203 writel(chl [all...] |
H A D | tifm_7xx1.c | 54 writel(TIFM_IRQ_ENABLE, fm->addr + FM_CLEAR_INTERRUPT_ENABLE); 69 writel(irq_status, fm->addr + FM_INTERRUPT_STATUS); 74 writel(TIFM_IRQ_ENABLE, fm->addr + FM_SET_INTERRUPT_ENABLE); 87 writel(0x0e00, sock_addr + SOCK_CONTROL); 101 writel(readl(sock_addr + SOCK_CONTROL) | TIFM_CTRL_LED, 109 writel((s_state & TIFM_CTRL_POWER_MASK) | 0x0c00, 121 writel(readl(sock_addr + SOCK_CONTROL) & (~TIFM_CTRL_LED), 129 writel((~TIFM_CTRL_POWER_MASK) & readl(sock_addr + SOCK_CONTROL), 175 writel(0x0e00, sock_addr + SOCK_CONTROL); 202 writel(TIFM_IRQ_FIFOMAS [all...] |
/drivers/net/ethernet/ |
H A D | korina.c | 144 writel(0, &ch->dmandptr); 145 writel(dma_addr, &ch->dmadptr); 152 writel(0x10, &ch->dmac); 157 writel(0, &ch->dmas); 160 writel(0, &ch->dmadptr); 161 writel(0, &ch->dmandptr); 166 writel(dma_addr, &ch->dmandptr); 244 writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), 260 writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), 299 writel( [all...] |
H A D | s6gmac.c | 503 writel(mask, pd->reg + S6_GMAC_STATCARRY(carry)); 529 writel(addrlo, pd->reg + S6_GMAC_HOST_DSTADDRLO(n)); 530 writel(addrhi, pd->reg + S6_GMAC_HOST_DSTADDRHI(n)); 531 writel(masklo, pd->reg + S6_GMAC_HOST_DSTMASKLO(n)); 532 writel(maskhi, pd->reg + S6_GMAC_HOST_DSTMASKHI(n)); 538 writel(0, pd->reg + S6_GMAC_MACCONF1); 547 writel(1 << S6_GMAC_MACCONF1_SYNCTX | 557 writel(1 << S6_GMAC_MACCONF1_SOFTRES, pd->reg + S6_GMAC_MACCONF1); 559 writel(1 << S6_GMAC_MACCONF1_TXENA | 1 << S6_GMAC_MACCONF1_RXENA, 561 writel( [all...] |
/drivers/net/ethernet/alteon/ |
H A D | acenic.c | 614 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl); 616 writel(readl(®s->CpuBCtrl) | CPU_HALT, ®s->CpuBCtrl); 621 writel(1, ®s->Mb0Lo); 853 writel(*(u32 *)(cmd), ®s->CmdRng[idx]); 856 writel(idx, ®s->CmdPrd); 883 writel(HW_RESET | (HW_RESET << 24), ®s->HostCtrl); 895 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)), 898 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)), 906 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl); 908 writel( [all...] |
/drivers/net/ethernet/amd/ |
H A D | amd8111e.c | 123 writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) | 152 writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) | 392 writel(VAL0|STINTEN, mmio+INTEN0); 393 writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout, 406 writel(VAL0|STINTEN,mmio+INTEN0); 407 writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout, 412 writel(0,mmio+STVAL); 413 writel(STINTEN, mmio+INTEN0); 414 writel(0, mmio +DLY_INT_B); 415 writel( [all...] |
/drivers/net/ethernet/nxp/ |
H A D | lpc_eth.c | 454 writel(tmp, LPC_ENET_SA2(pldat->net_base)); 456 writel(tmp, LPC_ENET_SA1(pldat->net_base)); 458 writel(tmp, LPC_ENET_SA0(pldat->net_base)); 495 writel(tmp, LPC_ENET_MAC2(pldat->net_base)); 498 writel(tmp, LPC_ENET_COMMAND(pldat->net_base)); 499 writel(LPC_IPGT_LOAD(0x15), LPC_ENET_IPGT(pldat->net_base)); 503 writel(tmp, LPC_ENET_MAC2(pldat->net_base)); 506 writel(tmp, LPC_ENET_COMMAND(pldat->net_base)); 507 writel(LPC_IPGT_LOAD(0x12), LPC_ENET_IPGT(pldat->net_base)); 511 writel(LPC_SUPP_SPEE [all...] |
/drivers/mmc/host/ |
H A D | tifm_sd.c | 150 writel(val, sock->addr + SOCK_MMCSD_DATA); 162 writel(val, sock->addr + SOCK_MMCSD_DATA); 185 writel(host->bounce_buf_data[0], 319 writel(sg_dma_address(sg) + dma_off, sock->addr + SOCK_DMA_ADDRESS); 321 writel((dma_blk_cnt << 8) | TIFM_DMA_TX | TIFM_DMA_EN, 324 writel((dma_blk_cnt << 8) | TIFM_DMA_EN, 386 writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH); 387 writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW); 388 writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND); 433 writel(TIFM_MMCSD_EOF [all...] |
/drivers/net/ethernet/allwinner/ |
H A D | sun4i-emac.c | 98 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); 111 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); 192 writel(0, db->membase + EMAC_CTL_REG); 194 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG); 268 writel(reg_val | EMAC_TX_MODE_ABORTED_FRAME_EN, 274 writel(reg_val | EMAC_MAC_CTL0_RX_FLOW_CTL_EN | 283 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); 286 writel(EMAC_MAC_IPGT_FULL_DUPLEX, db->membase + EMAC_MAC_IPGT_REG); 289 writel((EMAC_MAC_IPGR_IPG1 << 8) | EMAC_MAC_IPGR_IPG2, 293 writel((EMAC_MAC_CLRT_COLLISION_WINDO [all...] |
/drivers/spi/ |
H A D | spi-mxs.c | 98 writel(BM_SSP_CTRL0_LOCK_CS, 101 writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) | 107 writel(0x0, ssp->base + HW_SSP_CMD0); 108 writel(0x0, ssp->base + HW_SSP_CMD1); 314 writel(BM_SSP_CTRL0_IGNORE_CRC, 319 writel(BM_SSP_CTRL0_IGNORE_CRC, 323 writel(BM_SSP_CTRL0_XFER_COUNT, 325 writel(1, 328 writel(1, ssp->base + HW_SSP_XFER_SIZE); 332 writel(BM_SSP_CTRL0_REA [all...] |
/drivers/clocksource/ |
H A D | arm_global_timer.c | 97 writel(ctrl, gt_base + GT_CONTROL); 98 writel(lower_32_bits(counter), gt_base + GT_COMP0); 99 writel(upper_32_bits(counter), gt_base + GT_COMP1); 102 writel(delta, gt_base + GT_AUTO_INC); 107 writel(ctrl, gt_base + GT_CONTROL); 125 writel(ctrl, gt_base + GT_CONTROL); 213 writel(0, gt_base + GT_CONTROL); 214 writel(0, gt_base + GT_COUNTER0); 215 writel(0, gt_base + GT_COUNTER1); 217 writel(GT_CONTROL_TIMER_ENABL [all...] |
/drivers/media/rc/ |
H A D | sunxi-cir.c | 114 writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); 241 writel(REG_CTL_MD, ir->base+SUNXI_IR_CTL_REG); 244 writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE)|REG_CIR_ITHR(SUNXI_IR_RXIDLE), 248 writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG); 251 writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); 257 writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN | 263 writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG); 288 writel(0, ir->base + SUNXI_IR_RXINT_REG); 290 writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); 292 writel( [all...] |
H A D | st_rc.c | 115 writel(IRB_RX_OVERRUN_INT, 153 writel(IRB_RX_INTS, dev->rx_base + IRB_RX_INT_CLEAR); 174 writel(1, dev->rx_base + IRB_RX_POLARITY_INV); 177 writel(rx_sampling_freq_div, dev->base + IRB_SAMPLE_RATE_COMM); 187 writel(rx_max_symbol_per, dev->rx_base + IRB_MAX_SYM_PERIOD); 204 writel(IRB_RX_INTS, dev->rx_base + IRB_RX_INT_EN); 205 writel(0x01, dev->rx_base + IRB_RX_EN); 215 writel(0x00, dev->rx_base + IRB_RX_EN); 216 writel(0x00, dev->rx_base + IRB_RX_INT_EN); 349 writel( [all...] |
/drivers/phy/ |
H A D | phy-exynos5250-sata.c | 102 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); 108 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); 112 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); 116 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); 120 writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM); 125 writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM); 129 writel(val, sata_phy->regs + EXYNOS5_SATA_CTRL0); 133 writel(val, sata_phy->regs + EXYNOS5_SATA_MODE0); 142 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); 146 writel(va [all...] |
/drivers/rtc/ |
H A D | rtc-coh901331.c | 59 writel(1, rtap->virtbase + COH901331_IRQ_EVENT); 67 writel(0, rtap->virtbase + COH901331_IRQ_MASK); 96 writel(secs, rtap->virtbase + COH901331_SET_TIME); 122 writel(time, rtap->virtbase + COH901331_ALARM); 123 writel(alarm->enabled, rtap->virtbase + COH901331_IRQ_MASK); 135 writel(1, rtap->virtbase + COH901331_IRQ_MASK); 137 writel(0, rtap->virtbase + COH901331_IRQ_MASK); 228 writel(0, rtap->virtbase + COH901331_IRQ_MASK); 244 writel(rtap->irqmaskstore, rtap->virtbase + COH901331_IRQ_MASK); 258 writel( [all...] |
H A D | rtc-sun6i.c | 128 writel(val, chip->base + SUN6I_ALRM_IRQ_STA); 149 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, 153 writel(alrm_val, chip->base + SUN6I_ALRM_EN); 154 writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN); 155 writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG); 237 writel(0, chip->base + SUN6I_ALRM_COUNTER); 240 writel(time_gap, chip->base + SUN6I_ALRM_COUNTER); 301 writel(time, chip->base + SUN6I_RTC_HMS); 315 writel(date, chip->base + SUN6I_RTC_YMD); 382 writel( [all...] |
/drivers/tty/serial/ |
H A D | lpc32xx_hs.c | 136 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); 271 writel(LPC32XX_HSU_FE_INT, 294 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase)); 306 writel((u32) xmit->buf[xmit->tail], 321 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 338 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase)); 345 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase)); 349 writel(LPC32XX_HSU_RX_OE_INT, 362 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase)); 403 writel(tm [all...] |
H A D | netx-serial.c | 122 writel(val & ~CR_TIE, port->membase + UART_CR); 129 writel(val & ~CR_RIE, port->membase + UART_CR); 136 writel(val | CR_MSIE, port->membase + UART_CR); 144 writel(port->x_char, port->membase + UART_DR); 158 writel(xmit->buf[xmit->tail], port->membase + UART_DR); 172 writel( 209 writel(0, port->membase + UART_SR); 264 writel(0, port->membase + UART_IIR); 289 writel(val | RTS_CR_RTS, port->membase + UART_RTS_CR); 303 writel(line_c [all...] |
/drivers/irqchip/ |
H A D | irq-armada-370-xp.c | 87 writel(hwirq, main_int_base + 90 writel(hwirq, per_cpu_int_base + 99 writel(hwirq, main_int_base + 102 writel(hwirq, per_cpu_int_base + 233 writel(reg, per_cpu_int_base + 237 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 266 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); 288 writel(hw, per_cpu_int_base + 291 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); 326 writel((ma [all...] |
/drivers/block/ |
H A D | smart1,2.h | 44 writel(c->busaddr, h->vaddr + S42XX_REQUEST_PORT_OFFSET); 56 writel(0, h->vaddr + S42XX_REPLY_INTR_MASK_OFFSET); 59 writel( S42XX_INTR_OFF, 90 writel(0, h->vaddr + S42XX_REPLY_PORT_OFFSET); 123 writel(c->busaddr, h->vaddr + COMMAND_FIFO); 128 writel(val, h->vaddr + INTR_MASK);
|
/drivers/i2c/busses/ |
H A D | i2c-qup.c | 142 writel(QUP_RESET_STATE, qup->base + QUP_STATE); 151 writel(qup_err, qup->base + QUP_ERROR_FLAGS); 157 writel(QUP_RESET_STATE, qup->base + QUP_STATE); 162 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL); 165 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL); 217 writel(state, qup->base + QUP_STATE); 254 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE); 255 writel(total, qup->base + QUP_MX_WRITE_CNT); 258 writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN, 260 writel(tota [all...] |