Searched refs:reg (Results 151 - 175 of 2563) sorted by relevance

1234567891011>>

/drivers/clk/shmobile/
H A Dclk-r8a7740.c23 void __iomem *reg; member in struct:r8a7740_cpg
36 unsigned int reg; member in struct:div4_clk
70 unsigned int shift, reg; local
101 u32 value = clk_readl(cpg->reg + CPG_FRQCRC);
105 u32 value = clk_readl(cpg->reg + CPG_FRQCRA);
110 u32 value = clk_readl(cpg->reg + CPG_PLLC2CR);
114 u32 value = clk_readl(cpg->reg + CPG_USBCKCR);
128 reg = c->reg;
142 cpg->reg
[all...]
/drivers/pinctrl/spear/
H A Dpinctrl-spear320.c36 .reg = MODE_CONFIG_REG,
44 .reg = MODE_CONFIG_REG,
52 .reg = MODE_CONFIG_REG,
60 .reg = MODE_CONFIG_REG,
68 .reg = MODE_EXT_CONFIG_REG,
465 .reg = IP_SEL_PAD_60_69_REG,
469 .reg = IP_SEL_PAD_70_79_REG,
477 .reg = IP_SEL_PAD_80_89_REG,
483 .reg = IP_SEL_PAD_90_99_REG,
522 .reg
[all...]
/drivers/thermal/samsung/
H A Dexynos_tmu.c127 const struct exynos_tmu_registers *reg = data->pdata->registers; local
130 val_irq = readl(data->base + reg->tmu_intstat);
139 writel(val_irq, data->base + reg->tmu_intclear);
146 const struct exynos_tmu_registers *reg = pdata->registers; local
157 status = readb(data->base + reg->tmu_status);
165 for (i = 0; i < reg->triminfo_ctrl_count; i++) {
168 reg->triminfo_ctrl[i]);
171 reg->triminfo_ctrl[i]);
185 EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
188 trim_info = readl(data->base + reg
290 const struct exynos_tmu_registers *reg = pdata->registers; local
337 const struct exynos_tmu_registers *reg = pdata->registers; local
366 const struct exynos_tmu_registers *reg = pdata->registers; local
413 const struct exynos_tmu_registers *reg = pdata->registers; local
[all...]
/drivers/gpio/
H A Dgpio-mc9s08dz60.c38 static void mc9s_gpio_to_reg_and_bit(int offset, u8 *reg, u8 *bit) argument
40 *reg = 0x20 + offset / GPIO_NUM_PER_GROUP;
46 u8 reg, bit; local
50 mc9s_gpio_to_reg_and_bit(offset, &reg, &bit);
51 value = i2c_smbus_read_byte_data(mc9s->client, reg);
58 u8 reg, bit; local
61 mc9s_gpio_to_reg_and_bit(offset, &reg, &bit);
62 value = i2c_smbus_read_byte_data(mc9s->client, reg);
69 return i2c_smbus_write_byte_data(mc9s->client, reg, value);
/drivers/gpu/drm/gma500/
H A Dintel_i2c.c39 val = REG_READ(chan->reg);
49 val = REG_READ(chan->reg);
61 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE |
69 REG_WRITE(chan->reg, reserved | clock_bits);
81 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE |
91 REG_WRITE(chan->reg, reserved | data_bits);
96 * psb_intel_i2c_create - instantiate an Intel i2c bus using the specified GPIO reg
99 * @reg: GPIO reg to use
105 * Possible values for @reg includ
116 psb_intel_i2c_create(struct drm_device *dev, const u32 reg, const char *name) argument
[all...]
/drivers/media/dvb-frontends/
H A Da8293.c27 u8 reg[2]; member in struct:a8293_priv
80 priv->reg[0] = 0x10;
84 priv->reg[0] = 0x31;
88 priv->reg[0] = 0x38;
95 ret = a8293_wr(priv, &priv->reg[0], 1);
140 priv->reg[0] = 0x10;
141 ret = a8293_wr(priv, &priv->reg[0], 1);
146 priv->reg[1] = 0x82;
147 ret = a8293_wr(priv, &priv->reg[1], 1);
/drivers/mfd/
H A Dlm3533-ctrlbank.c78 u8 reg; local
87 reg = lm3533_ctrlbank_get_reg(cb, LM3533_REG_MAX_CURRENT_BASE);
88 ret = lm3533_write(cb->lm3533, reg, val);
99 u8 reg; \
105 reg = lm3533_ctrlbank_get_reg(cb, LM3533_REG_##_NAME##_BASE); \
106 ret = lm3533_write(cb->lm3533, reg, val); \
117 u8 reg; \
120 reg = lm3533_ctrlbank_get_reg(cb, LM3533_REG_##_NAME##_BASE); \
121 ret = lm3533_read(cb->lm3533, reg, val); \
H A Dstmpe-spi.c19 static int spi_reg_read(struct stmpe *stmpe, u8 reg) argument
22 int status = spi_w8r16(spi, reg | READ_CMD);
27 static int spi_reg_write(struct stmpe *stmpe, u8 reg, u8 val) argument
30 u16 cmd = (val << 8) | reg;
35 static int spi_block_read(struct stmpe *stmpe, u8 reg, u8 length, u8 *values) argument
40 ret = spi_reg_read(stmpe, reg + i);
49 static int spi_block_write(struct stmpe *stmpe, u8 reg, u8 length, argument
54 for (i = length; i > 0; i--, reg++) {
55 ret = spi_reg_write(stmpe, reg, *(values + i - 1));
/drivers/mmc/host/
H A Dsdhci.h271 u32 (*read_l)(struct sdhci_host *host, int reg);
272 u16 (*read_w)(struct sdhci_host *host, int reg);
273 u8 (*read_b)(struct sdhci_host *host, int reg);
274 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
275 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
276 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
303 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) argument
306 host->ops->write_l(host, val, reg);
308 writel(val, host->ioaddr + reg);
311 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) argument
319 sdhci_writeb(struct sdhci_host *host, u8 val, int reg) argument
327 sdhci_readl(struct sdhci_host *host, int reg) argument
335 sdhci_readw(struct sdhci_host *host, int reg) argument
343 sdhci_readb(struct sdhci_host *host, int reg) argument
353 sdhci_writel(struct sdhci_host *host, u32 val, int reg) argument
358 sdhci_writew(struct sdhci_host *host, u16 val, int reg) argument
363 sdhci_writeb(struct sdhci_host *host, u8 val, int reg) argument
368 sdhci_readl(struct sdhci_host *host, int reg) argument
373 sdhci_readw(struct sdhci_host *host, int reg) argument
378 sdhci_readb(struct sdhci_host *host, int reg) argument
[all...]
/drivers/net/ethernet/broadcom/genet/
H A Dbcmmii.c35 u32 reg; local
40 reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
41 reg |= MDIO_START_BUSY;
42 bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
61 u32 reg; local
66 reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
67 reg |= MDIO_START_BUSY;
68 bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
84 u32 reg, cmd_bits = 0; local
137 reg
173 u32 reg = 0; local
193 u32 reg; local
206 u32 reg; local
222 u32 reg; local
[all...]
/drivers/spi/
H A Dspi-bcm63xx-hsspi.c111 u32 reg; local
114 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
116 reg &= ~BIT(cs);
118 reg |= BIT(cs);
120 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
128 u32 reg; local
130 reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
131 __raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
134 reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
136 reg |
219 u32 reg; local
261 u32 reg; local
331 u32 reg, rate; local
[all...]
H A Dspi-sun4i.c89 static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg) argument
91 return readl(sspi->base_addr + reg);
94 static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value) argument
96 writel(value, sspi->base_addr + reg);
101 u32 reg, cnt; local
105 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
106 reg &= SUN4I_FIFO_STA_RF_CNT_MASK;
107 cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS;
136 u32 reg; local
138 reg
175 u32 reg; local
[all...]
/drivers/usb/host/
H A Duhci-hcd.h501 static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg) argument
503 return inl(uhci->io_addr + reg);
506 static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg) argument
508 outl(val, uhci->io_addr + reg);
511 static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg) argument
513 return inw(uhci->io_addr + reg);
516 static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg) argument
518 outw(val, uhci->io_addr + reg);
521 static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg) argument
523 return inb(uhci->io_addr + reg);
526 uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg) argument
548 uhci_readl(const struct uhci_hcd *uhci, int reg) argument
560 uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg) argument
572 uhci_readw(const struct uhci_hcd *uhci, int reg) argument
584 uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg) argument
596 uhci_readb(const struct uhci_hcd *uhci, int reg) argument
608 uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg) argument
[all...]
/drivers/video/fbdev/mb862xx/
H A Dmb862xxfbdrv.c207 unsigned long reg, sc; local
217 reg = inreg(disp, GC_DCM1);
218 reg &= ~GC_DCM01_DEN;
219 outreg(disp, GC_DCM1, reg);
223 reg = inreg(disp, GC_DCM1);
224 reg &= ~(GC_DCM01_CKS | GC_DCM01_RESV | GC_DCM01_SC);
225 reg |= sc << 8;
226 outreg(disp, GC_DCM1, reg);
230 reg = pack(d_pitch(&fbi->var) / GC_L0M_L0W_UNIT,
233 reg |
277 unsigned long reg; local
290 unsigned long reg; local
426 unsigned long reg; local
553 unsigned int reg; local
793 unsigned long reg; local
871 unsigned long reg; local
930 unsigned long reg; local
1138 unsigned long reg; local
[all...]
/drivers/base/regmap/
H A Dinternal.h38 unsigned int reg, unsigned int val);
39 void (*format_reg)(void *buf, unsigned int reg, unsigned int shift);
88 bool (*writeable_reg)(struct device *dev, unsigned int reg);
89 bool (*readable_reg)(struct device *dev, unsigned int reg);
90 bool (*volatile_reg)(struct device *dev, unsigned int reg);
91 bool (*precious_reg)(struct device *dev, unsigned int reg);
97 int (*reg_read)(void *context, unsigned int reg, unsigned int *val);
98 int (*reg_write)(void *context, unsigned int reg, unsigned int val);
105 /* number of bits to (left) shift the reg value when formatting*/
154 int (*read)(struct regmap *map, unsigned int reg, unsigne
189 unsigned int reg; member in struct:regmap_field
[all...]
H A Dregcache-flat.c32 cache[map->reg_defaults[i].reg] = map->reg_defaults[i].def;
46 unsigned int reg, unsigned int *value)
50 *value = cache[reg];
55 static int regcache_flat_write(struct regmap *map, unsigned int reg, argument
60 cache[reg] = value;
45 regcache_flat_read(struct regmap *map, unsigned int reg, unsigned int *value) argument
/drivers/clk/sunxi/
H A Dclk-sun6i-apb0.c37 void __iomem *reg; local
41 reg = devm_ioremap_resource(&pdev->dev, r);
42 if (IS_ERR(reg))
43 return PTR_ERR(reg);
52 0, reg, 0, 2, 0, sun6i_a31_apb0_divs,
H A Dclk-sun8i-apb0.c28 void __iomem *reg; local
32 reg = devm_ioremap_resource(&pdev->dev, r);
33 if (IS_ERR(reg))
34 return PTR_ERR(reg);
43 clk = clk_register_divider(&pdev->dev, clk_name, clk_parent, 0, reg,
/drivers/gpu/drm/mgag200/
H A Dmgag200_drv.h44 #define RREG8(reg) ioread8(((void __iomem *)mdev->rmmio) + (reg))
45 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)mdev->rmmio) + (reg))
46 #define RREG32(reg) ioread32(((void __iomem *)mdev->rmmio) + (reg))
47 #define WREG32(reg, v) iowrite32(v, ((void __iomem *)mdev->rmmio) + (reg))
52 #define WREG_ATTR(reg, v) \
55 WREG8(ATTR_INDEX, reg); \
[all...]
/drivers/pcmcia/
H A Di82092.c181 static unsigned char indirect_read(int socket, unsigned short reg) argument
187 reg += socket * 0x40;
189 outb(reg,port);
196 static unsigned short indirect_read16(int socket, unsigned short reg)
202 reg = reg + socket * 0x40;
204 outb(reg,port);
206 reg++;
207 outb(reg,port);
214 static void indirect_write(int socket, unsigned short reg, unsigne argument
226 indirect_setbit(int socket, unsigned short reg, unsigned char mask) argument
243 indirect_resetbit(int socket, unsigned short reg, unsigned char mask) argument
259 indirect_write16(int socket, unsigned short reg, unsigned short value) argument
463 unsigned char reg; local
[all...]
/drivers/net/ethernet/sfc/
H A Dtenxpress.c225 int rc, reg; local
233 reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
234 reg |= (1 << PMA_PMD_EXT_SSR_LBN);
235 efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
260 int reg; local
266 reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1);
267 if (!(reg & MDIO_AN_STAT1_LPABLE))
269 bad_lp = !(reg & MDIO_AN_STAT1_COMPLETE);
281 reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD,
283 reg
374 int reg; local
396 int reg; local
449 int reg; local
[all...]
/drivers/gpu/drm/nouveau/core/subdev/fb/
H A Dramfuc.h84 ramfuc_rd32(struct ramfuc *ram, struct ramfuc_reg *reg) argument
86 if (reg->sequence != ram->sequence)
87 reg->data = nv_rd32(ram->pfb, reg->addr);
88 return reg->data;
92 ramfuc_wr32(struct ramfuc *ram, struct ramfuc_reg *reg, u32 data) argument
96 reg->sequence = ram->sequence;
97 reg->data = data;
99 for (mask = reg->mask; mask > 0; mask = (mask & ~1) >> 1) {
101 nouveau_memx_wr32(ram->memx, reg
109 ramfuc_nuke(struct ramfuc *ram, struct ramfuc_reg *reg) argument
115 ramfuc_mask(struct ramfuc *ram, struct ramfuc_reg *reg, u32 mask, u32 data) argument
[all...]
/drivers/media/i2c/
H A Dupd64031a.c85 static u8 upd64031a_read(struct v4l2_subdev *sd, u8 reg) argument
90 if (reg >= sizeof(buf))
93 return buf[reg];
98 static void upd64031a_write(struct v4l2_subdev *sd, u8 reg, u8 val) argument
103 buf[0] = reg;
105 v4l2_dbg(1, debug, sd, "write reg: %02X val: %02X\n", reg, val);
107 v4l2_err(sd, "I/O error write 0x%02x/0x%02x\n", reg, val);
116 u8 reg = state->regs[R00]; local
119 upd64031a_write(sd, R00, reg |
157 upd64031a_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) argument
164 upd64031a_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) argument
[all...]
/drivers/net/wireless/b43/
H A Dphy_common.h24 #define B43_PHY_CCK(reg) ((reg) | B43_PHYROUTE_BASE)
26 #define B43_PHY_N(reg) ((reg) | B43_PHYROUTE_BASE)
28 #define B43_PHY_N_BMODE(reg) ((reg) | B43_PHYROUTE_N_BMODE)
30 #define B43_PHY_OFDM(reg) ((reg) | B43_PHYROUTE_OFDM_GPHY)
32 #define B43_PHY_EXTG(reg) ((reg) | B43_PHYROUTE_EXT_GPH
[all...]
/drivers/rtc/
H A Drtc-m48t86.c47 unsigned char reg; local
51 reg = ops->readbyte(M48T86_REG_B);
53 if (reg & M48T86_REG_B_DM) {
76 if (!(reg & M48T86_REG_B_H24))
85 unsigned char reg; local
89 reg = ops->readbyte(M48T86_REG_B);
92 reg |= M48T86_REG_B_SET | M48T86_REG_B_H24;
93 ops->writebyte(reg, M48T86_REG_B);
95 if (reg & M48T86_REG_B_DM) {
116 reg
124 unsigned char reg; local
149 unsigned char reg; local
[all...]

Completed in 8503 milliseconds

1234567891011>>