Searched defs:size (Results 176 - 200 of 2434) sorted by relevance

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/drivers/gpu/drm/bochs/
H A Dbochs_fbdev.c30 u32 size; local
33 size = mode_cmd->pitches[0] * mode_cmd->height;
34 ret = bochs_gem_create(dev, size, true, &gobj);
54 int size, ret; local
64 size = mode_cmd.pitches[0] * mode_cmd.height;
107 bochs->fb.size = size;
124 info->screen_size = size;
129 info->fix.smem_len = size;
H A Dbochs_hw.c54 unsigned long addr, size, mem, ioaddr, iosize; local
92 size = pci_resource_len(pdev, 0);
95 if (size != mem) {
97 size, mem);
98 size = min(size, mem);
106 bochs->fb_map = ioremap(addr, size);
112 bochs->fb_size = size;
115 DRM_INFO("Framebuffer size %ld kB @ 0x%lx, %s @ 0x%lx.\n",
116 size / 102
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/drivers/gpu/drm/
H A Ddrm_memory.c53 static void *agp_remap(unsigned long offset, unsigned long size, argument
57 PAGE_ALIGN(size) / PAGE_SIZE;
63 size = PAGE_ALIGN(size);
72 (offset + size))
115 static inline void *agp_remap(unsigned long offset, unsigned long size, argument
126 map->handle = agp_remap(map->offset, map->size, dev);
128 map->handle = ioremap(map->offset, map->size);
135 map->handle = agp_remap(map->offset, map->size, dev);
137 map->handle = ioremap_wc(map->offset, map->size);
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H A Ddrm_vma_manager.c42 * takes care to not overlap regions, size them appropriately and to not
75 * @size: Size of available address space range (page-based)
77 * Initialize a new offset-manager. The offset and area size available for the
78 * manager are given as @page_offset and @size. Both are interpreted as
87 unsigned long page_offset, unsigned long size)
91 drm_mm_init(&mgr->vm_addr_space_mm, page_offset, size);
121 * Find a node given a start address and object size. This returns the _best_
124 * whole requested area (given the size in number of pages as @pages).
184 offset = best->vm_node.start + best->vm_node.size;
221 * @pages: Allocation size visibl
86 drm_vma_offset_manager_init(struct drm_vma_offset_manager *mgr, unsigned long page_offset, unsigned long size) argument
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/drivers/gpu/drm/gma500/
H A Dgem.c91 * @size: the size requested
98 int psb_gem_create(struct drm_file *file, struct drm_device *dev, u64 size, argument
105 size = roundup(size, PAGE_SIZE);
109 r = psb_gtt_alloc_range(dev, size, "gem", 0, PAGE_SIZE);
111 dev_err(dev->dev, "no memory for %lld byte GEM object\n", size);
115 if (drm_gem_object_init(dev, &r->gem, size) != 0) {
118 dev_err(dev->dev, "GEM init failed for %lld\n", size);
127 &r->gem, size);
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/drivers/gpu/drm/mga/
H A Dmga_warp.c47 #define WARP_UCODE_SIZE(size) ALIGN(size, MGA_WARP_CODE_ALIGN)
57 unsigned int size; local
88 size = 0;
93 size += WARP_UCODE_SIZE(be16_to_cpu(rec->len));
102 size = PAGE_ALIGN(size);
103 DRM_DEBUG("MGA ucode size = %d bytes\n", size);
104 if (size > dev_pri
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/drivers/gpu/drm/nouveau/core/core/
H A Dparent.c78 nouveau_parent_lclass(struct nouveau_object *parent, u32 *lclass, int size) argument
88 if (++nr < size)
98 if (++nr < size)
115 int size, void **pobject)
122 NV_PARENT_CLASS, size, pobject);
111 nouveau_parent_create_(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, u32 pclass, struct nouveau_oclass *sclass, u64 engcls, int size, void **pobject) argument
H A Dsubdev.c91 int size, void **pobject)
97 NV_SUBDEV_CLASS, size, pobject);
87 nouveau_subdev_create_(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, u32 pclass, const char *subname, const char *sysname, int size, void **pobject) argument
/drivers/gpu/drm/nouveau/core/engine/copy/
H A Dnvc0.c100 struct nouveau_oclass *oclass, void *data, u32 size,
117 nv_falcon(priv)->code.size = sizeof(nvc0_pcopy_code);
119 nv_falcon(priv)->data.size = sizeof(nvc0_pcopy_data);
125 struct nouveau_oclass *oclass, void *data, u32 size,
142 nv_falcon(priv)->code.size = sizeof(nvc0_pcopy_code);
144 nv_falcon(priv)->data.size = sizeof(nvc0_pcopy_data);
99 nvc0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
124 nvc0_copy1_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
H A Dnve0.c84 struct nouveau_oclass *oclass, void *data, u32 size,
105 struct nouveau_oclass *oclass, void *data, u32 size,
126 struct nouveau_oclass *oclass, void *data, u32 size,
83 nve0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
104 nve0_copy1_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
125 nve0_copy2_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
/drivers/gpu/drm/nouveau/core/engine/crypt/
H A Dnv84.c47 struct nouveau_oclass *oclass, void *data, u32 size,
144 struct nouveau_oclass *oclass, void *data, u32 size,
45 nv84_crypt_object_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
143 nv84_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
H A Dnv98.c122 struct nouveau_oclass *oclass, void *data, u32 size,
139 nv_falcon(priv)->code.size = sizeof(nv98_pcrypt_code);
141 nv_falcon(priv)->data.size = sizeof(nv98_pcrypt_data);
121 nv98_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
/drivers/gpu/drm/nouveau/core/engine/device/
H A Dctrl.c37 void *data, u32 size)
45 nv_ioctl(object, "control pstate info size %d\n", size);
71 void *data, u32 size)
84 nv_ioctl(object, "control pstate attr size %d\n", size);
145 void *data, u32 size)
153 nv_ioctl(object, "control pstate user size %d\n", size);
175 void *data, u32 size)
36 nouveau_control_mthd_pstate_info(struct nouveau_object *object, void *data, u32 size) argument
70 nouveau_control_mthd_pstate_attr(struct nouveau_object *object, void *data, u32 size) argument
144 nouveau_control_mthd_pstate_user(struct nouveau_object *object, void *data, u32 size) argument
174 nouveau_control_mthd(struct nouveau_object *object, u32 mthd, void *data, u32 size) argument
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/drivers/gpu/drm/nouveau/core/engine/dmaobj/
H A Dbase.c72 u32 size = *psize; local
80 nv_ioctl(parent, "create dma size %d\n", *psize);
94 *psize = size;
105 if (dmaobj->limit >= pfb->ram->size - instmem->reserved)
149 struct nouveau_oclass *oclass, void *data, u32 size,
148 _nvkm_dmaeng_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
H A Dnv04.c87 struct nouveau_oclass *oclass, void *data, u32 size,
95 ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
97 if (ret || (ret = -ENOSYS, size))
86 nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
H A Dnv50.c88 struct nouveau_oclass *oclass, void *data, u32 size,
99 ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
105 nv_ioctl(parent, "create nv50 dma size %d\n", size);
116 if (size == 0) {
87 nv50_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
H A Dnvc0.c77 struct nouveau_oclass *oclass, void *data, u32 size,
88 ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
94 nv_ioctl(parent, "create gf100 dma size %d\n", size);
102 if (size == 0) {
76 nvc0_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
H A Dnvd0.c81 struct nouveau_oclass *oclass, void *data, u32 size,
92 ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
98 nv_ioctl(parent, "create gf110 dma size %d\n", size);
105 if (size == 0) {
80 nvd0_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
/drivers/gpu/drm/nouveau/core/engine/fifo/
H A Dnv17.c65 struct nouveau_oclass *oclass, void *data, u32 size,
75 nv_ioctl(parent, "create channel dma size %d\n", size);
155 struct nouveau_oclass *oclass, void *data, u32 size,
63 nv17_fifo_chan_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
154 nv17_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
/drivers/gpu/drm/nouveau/core/engine/mpeg/
H A Dnv40.c49 u32 size = dma1 + 1; local
59 nv_wr32(priv, 0x00b324, size);
65 nv_wr32(priv, 0x00b364, size);
72 nv_wr32(priv, 0x00b374, size);
113 struct nouveau_oclass *oclass, void *data, u32 size,
112 nv40_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
/drivers/gpu/drm/nouveau/core/engine/perfmon/
H A Dnv40.c112 struct nouveau_oclass *oclass, void *data, u32 size,
111 nv40_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
H A Dnvc0.c115 struct nouveau_oclass *oclass, void *data, u32 size,
114 nvc0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
/drivers/gpu/drm/nouveau/core/engine/software/
H A Dnv04.c45 void *data, u32 size)
55 void *args, u32 size)
83 struct nouveau_oclass *oclass, void *data, u32 size,
120 struct nouveau_oclass *oclass, void *data, u32 size,
44 nv04_software_set_ref(struct nouveau_object *object, u32 mthd, void *data, u32 size) argument
54 nv04_software_flip(struct nouveau_object *object, u32 mthd, void *args, u32 size) argument
81 nv04_software_context_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
119 nv04_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
H A Dnv10.c44 void *args, u32 size)
71 struct nouveau_oclass *oclass, void *data, u32 size,
102 struct nouveau_oclass *oclass, void *data, u32 size,
43 nv10_software_flip(struct nouveau_object *object, u32 mthd, void *args, u32 size) argument
69 nv10_software_context_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
101 nv10_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument
/drivers/gpu/drm/nouveau/core/subdev/bar/
H A Dbase.c41 struct nouveau_oclass *oclass, void *data, u32 size,
60 (u32)barobj->vma.offset, mem->size << 12);
39 nouveau_barobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) argument

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