| /drivers/clk/samsung/ |
| H A D | clk-exynos-audss.c | 81 int i, ret = 0; local
180 ret = PTR_ERR(clk_table[i]);
185 ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
187 if (ret) {
206 return ret;
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| H A D | clk-exynos-clkout.c | 62 int ret; local
113 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &clkout->data);
114 if (ret)
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| H A D | clk-pll.c | 1154 int ret, len; local
1284 ret = clk_register_clkdev(clk, pll_clk->alias, pll_clk->dev_name);
1285 if (ret)
1287 __func__, pll_clk->name, ret);
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| H A D | clk-s3c2410-dclk.c | 76 int ret = 0; local
81 return ret;
242 int ret, i; local
308 ret = PTR_ERR(clk_table[i]);
312 ret = clk_register_clkdev(clk_table[MUX_DCLK0], "dclk0", NULL);
313 if (!ret)
314 ret = clk_register_clkdev(clk_table[MUX_DCLK1], "dclk1", NULL);
315 if (!ret)
316 ret = clk_register_clkdev(clk_table[MUX_CLKOUT0],
318 if (!ret)
[all...] |
| H A D | clk-s3c2412.c | 260 int ret; local
296 ret = register_restart_handler(&s3c2412_restart_handler);
297 if (ret)
298 pr_warn("cannot register restart handler, %d\n", ret);
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| H A D | clk-s3c2443.c | 395 int ret; local
466 ret = register_restart_handler(&s3c2443_restart_handler);
467 if (ret)
468 pr_warn("cannot register restart handler, %d\n", ret);
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| H A D | clk-s5pv210-audss.c | 69 int i, ret = 0; local
170 ret = PTR_ERR(clk_table[i]);
175 ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
177 if (ret) {
194 return ret;
|
| H A D | clk.c | 101 unsigned int idx, ret; local
122 ret = clk_register_clkdev(clk, list->alias, list->dev_name);
123 if (ret)
134 unsigned int idx, ret; local
151 ret = clk_register_clkdev(clk, list->name, NULL);
152 if (ret)
184 unsigned int idx, ret; local
201 ret = clk_register_clkdev(clk, list->alias,
203 if (ret)
216 unsigned int idx, ret; local
255 unsigned int idx, ret; local
[all...] |
| /drivers/clk/shmobile/ |
| H A D | clk-div6.c | 123 int ret; local
146 ret = of_property_read_string(np, "clock-output-names", &name);
147 if (ret < 0) {
|
| H A D | clk-mstp.c | 197 int ret; local
200 ret = of_property_read_string_index(np, "clock-output-names",
202 if (ret < 0 || strlen(name) == 0)
206 ret = of_property_read_u32_index(np, idxname, i, &clkidx);
207 if (parent_name == NULL || ret < 0)
|
| /drivers/clk/st/ |
| H A D | clk-flexgen.c | 142 int ret = 0; local
150 ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * primary_div);
152 return ret;
|
| H A D | clkgen-mux.c | 95 int ret = 0; local
99 ret = clk_mux_ops.set_parent(mux_hw, genamux->muxsel);
100 if (ret)
101 return ret;
|
| /drivers/clk/tegra/ |
| H A D | clk-pll.c | 330 int ret; local
337 ret = clk_pll_wait_for_lock(pll);
342 return ret;
423 int ret; local
468 ret = _p_div_to_hw(hw, 1 << p_div);
469 if (ret < 0)
470 return ret;
472 cfg->p = ret;
567 int state, ret = 0; local
581 ret
593 int ret = 0; local
878 int ret; local
982 int ret = 0; local
1006 int ret = 0, p_div; local
1029 int state, ret = 0; local
1074 int ret = 0; local
1165 int state, ret = 0; local
1230 int state, ret = 0; local
1286 int ret; local
[all...] |
| /drivers/clk/ti/ |
| H A D | clk-dra7-atl.c | 220 int ret = 0; local
264 ret = of_property_read_u32(cfg_node, "bws",
266 ret |= of_property_read_u32(cfg_node, "aws",
268 if (!ret) {
287 return ret;
|
| H A D | gate.c | 68 int ret; local
71 ret = omap2_dflt_clk_enable(clk);
78 if (!ret) {
90 return ret;
|
| /drivers/clk/ux500/ |
| H A D | abx500-clk.c | 25 int ret; local
39 ret = ab8500_sysctrl_set(AB8500_SWATCTRL, AB8500_SWATCTRL_SWATENABLE);
40 if (ret)
41 return ret;
105 int ret; local
108 ret = ab8500_reg_clks(&pdev->dev);
110 ret = ab8540_reg_clks(&pdev->dev);
112 ret = ab9540_reg_clks(&pdev->dev);
118 return ret;
|
| H A D | clk-prcmu.c | 32 int ret; local
35 ret = prcmu_request_clock(clk->cg_sel, true);
36 if (!ret)
39 return ret;
|
| H A D | clk-sysctrl.c | 38 int ret; local
41 ret = ab8500_sysctrl_write(clk->reg_sel[0], clk->reg_mask[0],
44 if (!ret && clk->enable_delay_us)
47 return ret;
69 int ret = 0; local
72 ret = ab8500_sysctrl_clear(clk->reg_sel[old_index],
74 if (ret)
75 return ret;
79 ret = ab8500_sysctrl_write(clk->reg_sel[index],
82 if (ret) {
[all...] |
| /drivers/clk/zynq/ |
| H A D | clkc.c | 222 int ret; local
255 ret = of_property_read_u32(np, "ps-clk-frequency", &tmp);
256 if (ret) {
|
| /drivers/clocksource/ |
| H A D | acpi_pm.c | 237 int ret; local
239 ret = kstrtouint(arg, 16, &base);
240 if (ret)
241 return ret;
|
| H A D | arm_arch_timer.c | 622 int ret; local
639 ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
640 if (ret) {
645 return ret;
|
| H A D | cs5535-clockevt.c | 141 int ret; local
159 ret = setup_irq(timer_irq, &mfgptirq);
160 if (ret) {
|
| H A D | em_sti.c | 78 int ret; local
81 ret = clk_prepare_enable(p->clk);
82 if (ret) {
84 return ret;
167 int ret = 0; local
172 ret = em_sti_enable(p);
174 if (!ret)
178 return ret;
208 int ret; local
211 ret
[all...] |
| H A D | meson6_timer.c | 128 int ret, irq; local
156 ret = setup_irq(irq, &meson6_timer_irq);
157 if (ret)
|
| H A D | moxart_timer.c | 121 int ret, irq; local
133 ret = setup_irq(irq, &moxart_timer_irq);
134 if (ret)
|