| /drivers/net/wireless/rtlwifi/rtl8821ae/ |
| H A D | hw.c | 2829 u8 upper, lower;
2831 upper = pwrinfo5g.index_bw40_base[rf_path][index];
2834 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2917 u8 upper, lower; local
2919 upper = pwrinfo5g.index_bw40_base[rf_path][index];
2922 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
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| /drivers/net/ethernet/intel/ixgbevf/ |
| H A D | ixgbevf_main.c | 358 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
497 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
506 len = le16_to_cpu(rx_desc->wb.upper.length);
574 rx_desc->wb.upper.status_error = 0;
586 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
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| /drivers/net/wireless/rtlwifi/rtl8192ee/ |
| H A D | hw.c | 1964 u8 upper, lower; local
1967 upper = pwr5g.index_bw40_base[rf][idx];
1970 efu->txpwr_5g_bw80base[rf][i] = (upper + lower) / 2;
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| /drivers/gpu/drm/radeon/ |
| H A D | radeon_drv.h | 178 u32 upper; member in struct:radeon_surface
185 u32 upper; member in struct:radeon_virt_surface
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| /drivers/hwmon/ |
| H A D | lm93.c | 393 /* vid in mV, upper == 0 indicates low limit, otherwise upper limit */
394 static unsigned LM93_IN_REL_FROM_REG(u8 reg, int upper, int vid) argument
396 const long uv_offset = upper ? (((reg >> 4 & 0x0f) + 1) * 12500) :
406 * vid in mV , upper == 0 indicates low limit, otherwise upper limit
407 * upper also determines which nibble of the register is returned
410 static u8 LM93_IN_REL_TO_REG(unsigned val, int upper, int vid) argument
413 if (upper) {
487 /* temp3-temp4 (nr=2,3) use upper nibbl
[all...] |
| /drivers/net/ethernet/intel/e1000/ |
| H A D | e1000_main.c | 626 /* upper 16 bits has Tx packet buffer allocation size in KB */
3016 tx_desc->upper.data = cpu_to_le32(txd_upper);
3848 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
3867 tx_desc->upper.data = 0;
3925 eop_desc->upper.fields.status);
|
| H A D | e1000_ethtool.c | 1059 tx_desc->upper.data = 0;
|
| /drivers/net/ethernet/intel/ixgbe/ |
| H A D | ixgbe.h | 315 u16 limit; /* upper limit on feature indices */
545 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
|
| H A D | ixgbe_type.h | 2074 #define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
2187 #define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */
2188 #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
2368 } upper; member in struct:ixgbe_adv_rx_desc::__anon3313
|
| /drivers/scsi/ |
| H A D | scsi_debug.c | 2415 int lun_cnt, i, upper, num, n; local
2451 upper = (lun >> 8) & 0x3f;
2452 if (upper)
2454 (upper | (SAM2_LUN_ADDRESS_METHOD << 6));
|
| /drivers/net/ethernet/qlogic/qlge/ |
| H A D | qlge_main.c | 342 u32 upper = (addr[0] << 8) | addr[1]; local
364 ql_write32(qdev, MAC_ADDR_DATA, upper);
375 u32 upper = (addr[0] << 8) | addr[1]; local
396 ql_write32(qdev, MAC_ADDR_DATA, upper);
2655 /* We use the upper 32-bits to store the tx queue for this IO.
|
| /drivers/video/fbdev/aty/ |
| H A D | atyfb_base.c | 1151 u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync; local
1180 upper = v_total - v_sync_strt - v_sync_wid;
1269 var->upper_margin = upper;
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| /drivers/net/ethernet/intel/igb/ |
| H A D | igb_main.c | 523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1911 /* upper 16 bits has Tx packet buffer allocation size in KB */
6597 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6728 le32_to_cpu(rx_desc->wb.upper.status_error));
6898 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6900 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
|
| /drivers/net/ethernet/intel/e1000e/ |
| H A D | ethtool.c | 1232 tx_desc->upper.data = 0;
|
| /drivers/net/ethernet/broadcom/bnx2x/ |
| H A D | bnx2x_hsi.h | 118 u32 upper; member in struct:mac_addr
|