Searched defs:iobase (Results 76 - 100 of 112) sorted by relevance

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/drivers/staging/comedi/drivers/
H A Djr3_pci.c99 struct jr3_t __iomem *iobase; member in struct:jr3_pci_dev_private
380 struct jr3_t __iomem *iobase = devpriv->iobase; local
413 lo = &iobase->channel[subdev].program_lo[addr];
414 hi = &iobase->channel[subdev].program_hi[addr];
650 spriv->channel = &devpriv->iobase->channel[s->index].data;
673 spriv->channel, devpriv->iobase,
675 (char __iomem *)devpriv->iobase));
715 devpriv->iobase = pci_ioremap_bar(pcidev, 0);
716 if (!devpriv->iobase)
[all...]
H A Dpcmmio.c201 unsigned long iobase = dev->iobase; local
207 outb(val & 0xff, iobase + PCMMIO_PORT_REG(port + 0));
208 outb((val >> 8) & 0xff, iobase + PCMMIO_PORT_REG(port + 1));
209 outb((val >> 16) & 0xff, iobase + PCMMIO_PORT_REG(port + 2));
211 outb(PCMMIO_PAGE(page), iobase + PCMMIO_PAGE_LOCK_REG);
212 outb(val & 0xff, iobase + PCMMIO_PAGE_REG(0));
213 outb((val >> 8) & 0xff, iobase + PCMMIO_PAGE_REG(1));
214 outb((val >> 16) & 0xff, iobase + PCMMIO_PAGE_REG(2));
223 unsigned long iobase local
564 unsigned long iobase = dev->iobase; local
647 unsigned long iobase = dev->iobase; local
[all...]
H A Dadv_pci_dio.c426 data[1] |= inb(dev->iobase + d->addr + i) << (8 * i);
444 data[1] |= inw(dev->iobase + d->addr + 2 * i) << (16 * i);
460 dev->iobase + d->addr + i);
479 dev->iobase + d->addr + 2 * i);
502 data[0] = i8254_read(dev->iobase + d->addr + (SIZE_8254 * chip),
523 i8254_write(dev->iobase + d->addr + (SIZE_8254 * chip),
538 unsigned long iobase; local
545 iobase = dev->iobase + d->addr + (SIZE_8254 * chip);
549 ret = i8254_set_mode(iobase,
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H A Dcb_pcidas.c543 unsigned long iobase = devpriv->s5933_config; local
545 if (wait_for_nvram_ready(iobase) < 0)
549 iobase + AMCC_OP_REG_MCSR_NVCMD);
550 outb(address & 0xff, iobase + AMCC_OP_REG_MCSR_NVDATA);
552 iobase + AMCC_OP_REG_MCSR_NVCMD);
553 outb((address >> 8) & 0xff, iobase + AMCC_OP_REG_MCSR_NVDATA);
554 outb(MCSR_NV_ENABLE | MCSR_NV_READ, iobase + AMCC_OP_REG_MCSR_NVCMD);
556 if (wait_for_nvram_ready(iobase) < 0)
559 *data = inb(iobase + AMCC_OP_REG_MCSR_NVDATA);
932 unsigned long timer_base = dev->iobase
[all...]
H A Ddaqboard2000.c625 unsigned long iobase)
628 writew(data, dev->mmio + iobase + port * 2);
631 return readw(dev->mmio + iobase + port * 2);
623 daqboard2000_8255_cb(struct comedi_device *dev, int dir, int port, int data, unsigned long iobase) argument
H A Dplx9080.h383 static inline int plx9080_abort_dma(void __iomem *iobase, unsigned int channel) argument
391 dma_cs_addr = iobase + PLX_DMA1_CS_REG;
393 dma_cs_addr = iobase + PLX_DMA0_CS_REG;
/drivers/atm/
H A Dhorizon.c371 outl (cpu_to_le32 (data), dev->iobase + reg);
375 return le32_to_cpu (inl (dev->iobase + reg));
379 outw (cpu_to_le16 (data), dev->iobase + reg);
383 return le16_to_cpu (inw (dev->iobase + reg));
387 outsb (dev->iobase + reg, addr, len);
391 insb (dev->iobase + reg, addr, len);
2692 u32 iobase = pci_resource_start (pci_dev, 0); local
2703 if (!request_region(iobase, HRZ_IO_EXTENT, DEV_LABEL)) {
2731 iobase, irq, membase);
2761 dev->iobase
[all...]
H A Dambassador.h630 u32 iobase; member in struct:amb_dev
/drivers/char/tpm/
H A Dtpm.h67 void __iomem *iobase; /* ioremapped address */ member in struct:tpm_vendor_specific
/drivers/mfd/
H A Dsm501.c1048 resource_size_t iobase = sm->io_res->start + SM501_GPIO; local
1052 (unsigned long long)iobase);
1056 gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio");
1062 gpio->regs = ioremap(iobase, 0x20);
/drivers/mtd/spi-nor/
H A Dfsl-quadspi.c219 void __iomem *iobase; member in struct:fsl_qspi
253 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
254 writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
259 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
260 writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
269 reg = readl(q->iobase + QUADSPI_FR);
270 writel(reg, q->iobase + QUADSPI_FR);
281 void __iomem *base = q->iobase;
425 void __iomem *base = q->iobase;
481 tmp = readl(q->iobase
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/drivers/net/ethernet/3com/
H A D3c509.c288 unsigned int iobase; local
296 iobase = id_read_eeprom(8);
297 if_port = iobase >> 14;
298 ioaddr = 0x200 + ((iobase & 0x1f) << 4);
/drivers/net/ethernet/amd/
H A Datarilance.c220 struct lance_ioreg *iobase; member in struct:lance_private
534 IO = lp->iobase = (struct lance_ioreg *)ioaddr;
644 struct lance_ioreg *IO = lp->iobase;
733 struct lance_ioreg *IO = lp->iobase;
776 struct lance_ioreg *IO = lp->iobase;
863 IO = lp->iobase;
1051 struct lance_ioreg *IO = lp->iobase;
1078 struct lance_ioreg *IO = lp->iobase;
/drivers/net/ethernet/
H A Dethoc.c180 * @iobase: pointer to I/O memory region
200 void __iomem *iobase; member in struct:ethoc
239 return ioread32(dev->iobase + offset);
244 iowrite32(data, dev->iobase + offset);
1078 priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
1080 if (!priv->iobase) {
/drivers/net/hamradio/
H A Dbaycom_epp.c958 printk(KERN_INFO "%s: close epp at iobase 0x%lx irq %u\n",
1034 hi.data.mp.iobase = dev->base_addr;
1046 dev->base_addr = hi.data.mp.iobase;
1166 static int iobase[NR_PORTS] = { 0x378, }; variable
1170 module_param_array(iobase, int, NULL, 0);
1171 MODULE_PARM_DESC(iobase, "baycom io base address");
1217 dev->base_addr = iobase[i];
1222 iobase[i] = 0;
1279 iobase[nr_dev] = ints[1];
H A Dyam.c115 int iobase; member in struct:yam_port
164 #define RBR(iobase) (iobase+0)
165 #define THR(iobase) (iobase+0)
166 #define IER(iobase) (iobase+1)
167 #define IIR(iobase) (iobase+2)
168 #define FCR(iobase) (iobas
306 fpga_reset(int iobase) argument
328 fpga_write(int iobase, unsigned char wrd) argument
444 fpga_download(int iobase, int bitrate) argument
509 yam_check_uart(unsigned int iobase) argument
[all...]
/drivers/net/irda/
H A Dau1k_ir.c149 void __iomem *iobase; member in struct:au1k_private
199 (void)__raw_readl(p->iobase + ofs);
200 return __raw_readl(p->iobase + ofs);
206 __raw_writel(val, p->iobase + ofs);
933 aup->iobase = ioremap_nocache(r->start, resource_size(r));
934 if (!aup->iobase)
958 iounmap(aup->iobase);
980 iounmap(aup->iobase);
H A Dnsc-ircc.h277 static inline void switch_bank(int iobase, int bank) argument
279 outb(bank, iobase+BSR);
H A Dsmsc-ircc2.c210 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
360 static inline void register_bank(int iobase, int bank) argument
362 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
363 iobase + IRCC_MASTER);
750 int iobase = self->io.fir_base; local
752 register_bank(iobase, 0);
753 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
754 outb(0x00, iobase + IRCC_MASTER);
756 register_bank(iobase, 1);
757 outb(((inb(iobase
1129 int iobase; local
1250 int iobase = self->io.fir_base; local
1305 int iobase = self->io.fir_base; local
1350 int iobase = self->io.fir_base; local
1407 int iobase = self->io.fir_base; local
1478 int iobase; local
1511 int iobase, iir, lcra, lsr; local
1571 int iobase; local
1671 int iobase = self->io.fir_base; local
1933 int iobase; local
1956 int iobase; local
2016 smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len) argument
2114 int iobase = self->io.sir_base; local
2526 unsigned short iobase = conf->cfg_base; local
[all...]
H A Dvia-ircc.h285 static void SetMaxRxPacketSize(__u16 iobase, __u16 size) argument
291 WriteReg(iobase, I_CF_L_2, low);
292 WriteReg(iobase, I_CF_H_2, high);
300 static void SetFIFO(__u16 iobase, __u16 value) argument
304 WriteRegBit(iobase, 0x11, 0, 0);
305 WriteRegBit(iobase, 0x11, 7, 1);
308 WriteRegBit(iobase, 0x11, 0, 0);
309 WriteRegBit(iobase, 0x11, 7, 0);
312 WriteRegBit(iobase, 0x11, 0, 1);
313 WriteRegBit(iobase,
411 SetTimer(__u16 iobase, __u8 count) argument
419 SetSendByte(__u16 iobase, __u32 count) argument
431 ResetChip(__u16 iobase, __u8 type) argument
439 CkRxRecv(__u16 iobase, struct via_ircc_cb *self) argument
460 RxCurCount(__u16 iobase, struct via_ircc_cb * self) argument
476 GetRecvByte(__u16 iobase, struct via_ircc_cb * self) argument
533 ActClk(__u16 iobase, __u8 value) argument
543 ClkTx(__u16 iobase, __u8 Clk, __u8 Tx) argument
565 Wr_Byte(__u16 iobase, __u8 data) argument
591 Rd_Indx(__u16 iobase, __u8 addr, __u8 index) argument
655 Wr_Indx(__u16 iobase, __u8 addr, __u8 index, __u8 data) argument
676 ResetDongle(__u16 iobase) argument
690 SetSITmode(__u16 iobase) argument
702 SI_SetMode(__u16 iobase, int mode) argument
717 InitCard(__u16 iobase) argument
725 CommonInit(__u16 iobase) argument
750 SetBaudRate(__u16 iobase, __u32 rate) argument
787 SetPulseWidth(__u16 iobase, __u8 width) argument
801 SetSendPreambleCount(__u16 iobase, __u8 count) argument
[all...]
/drivers/pci/host/
H A Dpci-mvebu.c80 u8 iobase; member in struct:mvebu_sw_pci_bridge
351 phys_addr_t iobase; local
353 /* Are the new iobase/iolimit values invalid? */
354 if (port->bridge.iolimit < port->bridge.iobase ||
379 * specifications. iobase is the bus address, port->iowin_base
382 iobase = ((port->bridge.iobase & 0xF0) << 8) |
384 port->iowin_base = port->pcie->io.start + iobase;
387 iobase) + 1;
391 iobase);
[all...]
/drivers/scsi/
H A Du14-34f.c734 static int wait_on_busy(unsigned long iobase, unsigned int loop) { argument
736 while (inb(iobase + REG_LCL_INTR) & BSY_ASSERTED) {
H A Dwd7000.c246 int iobase; /* This adapter's I/O base address */ member in struct:adapter
301 unsigned iobase; /* I/O base address */ member in struct:__anon6227
676 configs[wd7000_card_num].iobase = ints[3];
709 if (configs[i].iobase == configs[j].iobase) {
717 "BUS_ON=%dns, BUS_OFF=%dns\n", configs[wd7000_card_num].irq, configs[wd7000_card_num].dma, configs[wd7000_card_num].iobase, configs[wd7000_card_num].bus_on * 125, configs[wd7000_card_num].bus_off * 125);
741 outb(host->control, host->iobase + ASC_CONTROL);
749 outb(host->control, host->iobase + ASC_CONTROL);
779 if (!WAIT(host->iobase + ASC_STAT, ASC_STATMASK, CMD_RDY, 0)) {
782 outb(*cmd, host->iobase
1383 unsigned iobase; local
[all...]
/drivers/staging/dgnc/
H A Ddgnc_driver.h244 ulong iobase; /* Start of io base of the card */ member in struct:dgnc_board
/drivers/tty/serial/jsm/
H A Djsm.h158 u64 iobase; /* Start of io base of the card */ member in struct:jsm_board

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