Searched refs:reg (Results 76 - 100 of 2563) sorted by relevance

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/drivers/net/can/
H A Dbfin_can.c66 struct bfin_can_regs __iomem *reg = priv->membase; local
81 bfin_write(&reg->clock, clk);
82 bfin_write(&reg->timing, timing);
92 struct bfin_can_regs __iomem *reg = priv->membase; local
97 bfin_write(&reg->mbim1, 0);
98 bfin_write(&reg->mbim2, 0);
99 bfin_write(&reg->gim, 0);
102 bfin_write(&reg->control, SRS | CCR);
104 bfin_write(&reg->control, CCR);
106 while (!(bfin_read(&reg
154 struct bfin_can_regs __iomem *reg = priv->membase; local
227 struct bfin_can_regs __iomem *reg = priv->membase; local
240 struct bfin_can_regs __iomem *reg = priv->membase; local
285 struct bfin_can_regs __iomem *reg = priv->membase; local
332 struct bfin_can_regs __iomem *reg = priv->membase; local
418 struct bfin_can_regs __iomem *reg = priv->membase; local
638 struct bfin_can_regs __iomem *reg = priv->membase; local
661 struct bfin_can_regs __iomem *reg = priv->membase; local
[all...]
/drivers/mfd/
H A Dmax77686.c53 unsigned int reg)
55 return reg < MAX77802_REG_PMIC_END;
59 unsigned int reg)
61 return (reg >= MAX77802_RTC_INT && reg < MAX77802_RTC_END);
64 static bool max77802_is_accessible_reg(struct device *dev, unsigned int reg) argument
66 return (max77802_pmic_is_accessible_reg(dev, reg) ||
67 max77802_rtc_is_accessible_reg(dev, reg));
70 static bool max77802_pmic_is_precious_reg(struct device *dev, unsigned int reg) argument
72 return (reg
52 max77802_pmic_is_accessible_reg(struct device *dev, unsigned int reg) argument
58 max77802_rtc_is_accessible_reg(struct device *dev, unsigned int reg) argument
76 max77802_rtc_is_precious_reg(struct device *dev, unsigned int reg) argument
83 max77802_is_precious_reg(struct device *dev, unsigned int reg) argument
89 max77802_pmic_is_volatile_reg(struct device *dev, unsigned int reg) argument
96 max77802_rtc_is_volatile_reg(struct device *dev, unsigned int reg) argument
108 max77802_is_volatile_reg(struct device *dev, unsigned int reg) argument
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H A Dwm8350-gpio.c52 u16 reg; local
57 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1)
60 reg | ((func & 0xf) << 0));
63 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1)
66 reg | ((func & 0xf) << 4));
69 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1)
72 reg | ((func & 0xf) << 8));
75 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1)
78 reg | ((func & 0xf) << 12));
81 reg
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/drivers/net/dsa/
H A Dmv88e6xxx.h46 int reg; member in struct:mv88e6xxx_hw_stat
49 int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg);
50 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg);
52 int reg, u16 val);
53 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val);
75 #define REG_READ(addr, reg) \
79 __ret = mv88e6xxx_reg_read(ds, addr, reg); \
85 #define REG_WRITE(addr, reg, val) \
89 __ret = mv88e6xxx_reg_write(ds, addr, reg, val); \
H A Dbcm_sf2.c116 offset = s->reg + CORE_P_MIB_OFFSET(port);
142 u32 reg; local
152 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
153 reg |= (1 << cpu_port);
154 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
161 u32 reg, val; local
164 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
165 reg &= ~P_TXQ_PSM_VDD(port);
166 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
169 reg
226 u32 reg; local
241 u32 reg; local
274 u32 off, reg; local
324 u32 reg; local
383 u32 reg; local
411 u32 reg, rev; local
546 u32 reg; local
609 u32 reg; local
688 u32 reg; local
771 u32 reg; local
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/drivers/net/ethernet/intel/ixgb/
H A Dixgb_ethtool.c225 u32 *reg = p; local
226 u32 *reg_start = reg;
235 *reg++ = IXGB_READ_REG(hw, CTRL0); /* 0 */
236 *reg++ = IXGB_READ_REG(hw, CTRL1); /* 1 */
237 *reg++ = IXGB_READ_REG(hw, STATUS); /* 2 */
238 *reg++ = IXGB_READ_REG(hw, EECD); /* 3 */
239 *reg++ = IXGB_READ_REG(hw, MFS); /* 4 */
242 *reg++ = IXGB_READ_REG(hw, ICR); /* 5 */
243 *reg++ = IXGB_READ_REG(hw, ICS); /* 6 */
244 *reg
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/drivers/acpi/acpica/
H A Dhwregs.c70 * PARAMETERS: reg - GAS register structure
83 acpi_hw_validate_register(struct acpi_generic_address *reg, argument
89 if (!reg) {
98 ACPI_MOVE_64_TO_64(address, &reg->address);
105 if ((reg->space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) &&
106 (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO)) {
108 "Unsupported address space: 0x%X", reg->space_id));
114 if ((reg->bit_width != 8) &&
115 (reg->bit_width != 16) &&
116 (reg
155 acpi_hw_read(u32 *value, struct acpi_generic_address *reg) argument
212 acpi_hw_write(u32 value, struct acpi_generic_address *reg) argument
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/drivers/clk/hisilicon/
H A Dclkgate-separated.c52 u32 reg; local
57 reg = BIT(sclk->bit_idx);
58 writel_relaxed(reg, sclk->enable);
69 u32 reg; local
74 reg = BIT(sclk->bit_idx);
75 writel_relaxed(reg, sclk->enable + CLKGATE_SEPERATED_DISABLE);
84 u32 reg; local
87 reg = readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS);
88 reg &= BIT(sclk->bit_idx);
90 return reg
99 hisi_register_clkgate_sep(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock) argument
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/drivers/net/
H A Dmdio.c99 int devad, reg; local
103 reg = mdio->mdio_read(mdio->dev, mdio->prtad,
105 return reg >= 0 && !(reg & MDIO_STAT2_RXFAULT);
121 reg = mdio->mdio_read(mdio->dev, mdio->prtad,
123 if (reg < 0 ||
124 (reg & (MDIO_STAT1_FAULT | MDIO_STAT1_LSTATUS)) !=
154 int reg; local
156 reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_AN, addr);
157 if (reg
190 int reg; local
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/drivers/gpu/drm/nouveau/dispnv04/
H A Dtvnv17.h130 static inline void nv_write_ptv(struct drm_device *dev, uint32_t reg, argument
134 nvif_wr32(device, reg, val);
137 static inline uint32_t nv_read_ptv(struct drm_device *dev, uint32_t reg) argument
140 return nvif_rd32(device, reg);
143 static inline void nv_write_tv_enc(struct drm_device *dev, uint8_t reg, argument
146 nv_write_ptv(dev, NV_PTV_TV_INDEX, reg);
150 static inline uint8_t nv_read_tv_enc(struct drm_device *dev, uint8_t reg) argument
152 nv_write_ptv(dev, NV_PTV_TV_INDEX, reg);
156 #define nv_load_ptv(dev, state, reg) \
157 nv_write_ptv(dev, NV_PTV_OFFSET + 0x##reg, stat
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/drivers/phy/
H A Dphy-exynos5-usbdrd.c188 static unsigned int exynos5_rate_to_clk(unsigned long rate, u32 *reg) argument
194 *reg = EXYNOS5_FSEL_9MHZ6;
197 *reg = EXYNOS5_FSEL_10MHZ;
200 *reg = EXYNOS5_FSEL_12MHZ;
203 *reg = EXYNOS5_FSEL_19MHZ2;
206 *reg = EXYNOS5_FSEL_20MHZ;
209 *reg = EXYNOS5_FSEL_24MHZ;
212 *reg = EXYNOS5_FSEL_50MHZ;
243 static u32 reg; local
247 reg
289 static u32 reg; local
308 u32 reg; local
323 u32 reg; local
348 u32 reg; local
410 u32 reg; local
[all...]
/drivers/watchdog/
H A Dwm8350_wdt.c44 u16 reg; local
55 reg = wm8350_reg_read(wm8350, WM8350_SYSTEM_CONTROL_2);
56 reg &= ~WM8350_WDOG_TO_MASK;
57 reg |= wm8350_wdt_cfgs[i].val;
58 ret = wm8350_reg_write(wm8350, WM8350_SYSTEM_CONTROL_2, reg);
71 u16 reg; local
76 reg = wm8350_reg_read(wm8350, WM8350_SYSTEM_CONTROL_2);
77 reg &= ~WM8350_WDOG_MODE_MASK;
78 reg |= 0x20;
79 ret = wm8350_reg_write(wm8350, WM8350_SYSTEM_CONTROL_2, reg);
91 u16 reg; local
110 u16 reg; local
[all...]
/drivers/media/i2c/smiapp/
H A Dsmiapp-regs.c81 static int ____smiapp_read(struct smiapp_sensor *sensor, u16 reg, argument
87 u16 offset = reg;
140 static int ____smiapp_read_8only(struct smiapp_sensor *sensor, u16 reg, argument
151 rval = ____smiapp_read(sensor, reg + i, 1, &val8);
164 static int __smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val, argument
168 u8 len = SMIAPP_REG_WIDTH(reg);
176 rval = ____smiapp_read(sensor, SMIAPP_REG_ADDR(reg), len, val);
178 rval = ____smiapp_read_8only(sensor, SMIAPP_REG_ADDR(reg), len,
183 if (reg & SMIAPP_REG_FLAG_FLOAT)
189 int smiapp_read_no_quirk(struct smiapp_sensor *sensor, u32 reg, u3 argument
197 smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val) argument
211 smiapp_read_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val) argument
225 smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val) argument
295 smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val) argument
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/drivers/scsi/qla4xxx/
H A Dql4_dbg.c47 readw(&ha->reg->mailbox[i]));
52 readw(&ha->reg->flash_address));
55 readw(&ha->reg->flash_data));
58 readw(&ha->reg->ctrl_status));
63 readw(&ha->reg->u1.isp4010.nvram));
67 readw(&ha->reg->u1.isp4022.intr_mask));
70 readw(&ha->reg->u1.isp4022.nvram));
73 readw(&ha->reg->u1.isp4022.semaphore));
77 readw(&ha->reg->req_q_in));
80 readw(&ha->reg
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/drivers/media/dvb-frontends/
H A Dstb0899_drv.c224 static int _stb0899_read_reg(struct stb0899_state *state, unsigned int reg) argument
228 u8 b0[] = { reg >> 8, reg & 0xff };
250 reg, ret);
256 reg, buf);
261 int stb0899_read_reg(struct stb0899_state *state, unsigned int reg) argument
265 result = _stb0899_read_reg(state, reg);
271 if ((reg != 0xf2ff) && (reg != 0xf6ff) &&
272 (((reg
451 stb0899_read_regs(struct stb0899_state *state, unsigned int reg, u8 *buf, u32 count) argument
502 stb0899_write_regs(struct stb0899_state *state, unsigned int reg, u8 *data, u32 count) argument
552 stb0899_write_reg(struct stb0899_state *state, unsigned int reg, u8 data) argument
650 u32 reg; local
687 u8 reg = 0; local
706 u8 reg, i; local
731 u8 reg = 0; local
749 u8 reg, length = 0, i; local
780 u8 reg = 0; local
797 u8 reg, old_state; local
837 u8 f22_tx, reg; local
970 u32 reg; local
1015 u32 reg; local
1069 u8 reg; local
1212 u8 div, reg; local
1307 u8 reg; local
1415 u32 reg; local
[all...]
/drivers/net/phy/
H A Dbroadcom.c212 int reg, err; local
214 reg = phy_read(phydev, MII_BCM54XX_ECR);
215 if (reg < 0)
216 return reg;
219 reg |= MII_BCM54XX_ECR_IM;
220 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
225 reg = ~(MII_BCM54XX_INT_DUPLEX |
228 err = phy_write(phydev, MII_BCM54XX_IMR, reg);
249 int err, reg; local
257 reg
339 int reg; local
351 int reg, err; local
375 u16 reg; local
401 brcm_phy_setbits(struct phy_device *phydev, int reg, int set) argument
414 int reg, err, err2, brcmtest; local
484 int reg; local
496 int reg, err; local
[all...]
H A Dmdio-bitbang.c97 static void mdiobb_cmd(struct mdiobb_ctrl *ctrl, int op, u8 phy, u8 reg) argument
128 mdiobb_send_num(ctrl, reg, 5);
140 unsigned int reg = addr & 0xFFFF; local
147 mdiobb_send_num(ctrl, reg, 16);
155 static int mdiobb_read(struct mii_bus *bus, int phy, int reg) argument
160 if (reg & MII_ADDR_C45) {
161 reg = mdiobb_cmd_addr(ctrl, phy, reg);
162 mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg);
164 mdiobb_cmd(ctrl, MDIO_READ, phy, reg);
184 mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val) argument
[all...]
/drivers/usb/gadget/udc/
H A Dfotg210-udc.c33 u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1);
39 iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1);
44 u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1);
50 iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1);
55 u32 value = ioread32(fotg210->reg + FOTG210_DCFESR);
58 iowrite32(value, fotg210->reg + FOTG210_DCFESR);
95 val = ioread32(fotg210->reg + FOTG210_EPMAP);
98 iowrite32(val, fotg210->reg + FOTG210_EPMAP);
101 val = ioread32(fotg210->reg + FOTG210_FIFOMAP);
104 iowrite32(val, fotg210->reg
180 void __iomem *reg; local
464 void __iomem *reg; local
485 void __iomem *reg; local
717 void __iomem *reg; local
889 void __iomem *reg = fotg210->reg + FOTG210_DISGR2; local
948 void __iomem *reg = fotg210->reg + FOTG210_DISGR0; local
986 void __iomem *reg = fotg210->reg + FOTG210_DISGR1; local
1010 u32 reg = ioread32(fotg210->reg + FOTG210_PHYTMSR); local
[all...]
/drivers/gpu/drm/sis/
H A Dsis_drv.h53 #define SIS_READ(reg) DRM_READ32(SIS_BASE, reg)
54 #define SIS_WRITE(reg, val) DRM_WRITE32(SIS_BASE, reg, val)
/drivers/hwmon/
H A Dadt7x10.h20 int (*read_byte)(struct device *, u8 reg);
21 int (*write_byte)(struct device *, u8 reg, u8 data);
22 int (*read_word)(struct device *, u8 reg);
23 int (*write_word)(struct device *, u8 reg, u16 data);
/drivers/media/tuners/
H A Dm88ts2022_priv.h31 u8 reg; member in struct:m88ts2022_reg_val
/drivers/scsi/
H A Datari_scsi.h44 #define NCR5380_read(reg) atari_scsi_reg_read( reg )
45 #define NCR5380_write(reg, value) atari_scsi_reg_write( reg, value )
/drivers/net/ethernet/intel/i40e/
H A Di40e_diag.c33 * @reg: reg to be tested
37 u32 reg, u32 mask)
43 orig_val = rd32(hw, reg);
46 wr32(hw, reg, (pat & mask));
47 val = rd32(hw, reg);
50 "%s: reg pattern test failed - reg 0x%08x pat 0x%08x val 0x%08x\n",
51 __func__, reg, pat, val);
56 wr32(hw, reg, orig_va
36 i40e_diag_reg_pattern_test(struct i40e_hw *hw, u32 reg, u32 mask) argument
101 u32 reg, mask; local
[all...]
/drivers/char/tpm/
H A Dtpm_atmel.h43 const unsigned int *reg; local
58 reg = of_get_property(dn, "reg", &reglen);
66 address = ((unsigned long) reg[0] << 32) | reg[1];
68 address = reg[0];
72 ((unsigned long) reg[naddrc] << 32) | reg[naddrc + 1];
74 size = reg[naddrc];
/drivers/clk/shmobile/
H A Dclk-emev2.c73 u32 reg[2]; local
76 if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2)))
81 smu_base + reg[0], reg[1], 8, 0, &lock);
91 u32 reg[2]; local
94 if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2)))
99 smu_base + reg[0], reg[
[all...]

Completed in 489 milliseconds

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