Searched refs:timing (Results 76 - 100 of 124) sorted by relevance

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/drivers/ata/
H A Dpata_samsung_cf.c108 struct ata_timing timing; local
121 ata_timing_compute(adev, adev->pio_mode, &timing,
124 piotime = pata_s3c_setup_timing(info, &timing);
H A Dahci_xgene.c282 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); local
299 rc = sata_link_hardreset(link, timing, deadline, online,
H A Dsata_highbank.c395 * The other timing constants were kept the same as the stock AHCI driver.
402 static const unsigned long timing[] = { 5, 100, 500}; local
422 rc = sata_link_hardreset(link, timing, deadline, &online, NULL);
/drivers/mtd/nand/
H A Ddavinci_nand.c77 struct davinci_aemif_timing *timing; member in struct:davinci_nand_info
676 info->timing = pdata->timing;
H A Dfsl_ifc_nand.c453 int timing = IFC_FIR_OP_RB; local
455 timing = IFC_FIR_OP_RBCD;
459 (timing << IFC_NAND_FIR0_OP2_SHIFT),
/drivers/media/pci/zoran/
H A Dzoran_device.c349 tvn = zr->timing;
728 tvn = zr->timing;
1014 zr->codec->set_video(zr->codec, zr->timing, &cap,
1022 zr->vfe->set_video(zr->vfe, zr->timing, &cap,
1048 zr->vfe->set_video(zr->vfe, zr->timing, &cap,
1053 zr->codec->set_video(zr->codec, zr->timing, &cap,
1614 /* set up GPIO pins and guest bus timing */
H A Dzoran_card.c1004 zr->timing = zr->card.tvn[0];
1007 zr->timing = zr->card.tvn[1];
1010 zr->timing = zr->card.tvn[2];
1012 if (zr->timing == NULL) {
1018 zr->timing = zr->card.tvn[0];
/drivers/memory/
H A DKconfig40 functions of the driver includes re-configuring AC timing
/drivers/net/can/
H A Dgrcan.c412 u32 timing = 0; local
439 timing |= (bpr << GRCAN_CONF_BPR_BIT) & GRCAN_CONF_BPR;
440 timing |= (rsj << GRCAN_CONF_RSJ_BIT) & GRCAN_CONF_RSJ;
441 timing |= (ps1 << GRCAN_CONF_PS1_BIT) & GRCAN_CONF_PS1;
442 timing |= (ps2 << GRCAN_CONF_PS2_BIT) & GRCAN_CONF_PS2;
443 timing |= (scaler << GRCAN_CONF_SCALER_BIT) & GRCAN_CONF_SCALER;
444 netdev_info(dev, "setting timing=0x%x\n", timing);
445 grcan_write_bits(&regs->conf, timing, GRCAN_CONF_TIMING);
1649 /* Reset device to allow bit-timing t
[all...]
/drivers/net/wireless/iwlwifi/dvm/
H A Ddevices.c415 u16 beacon_interval = le16_to_cpu(ctx->timing.beacon_interval);
576 u16 beacon_interval = le16_to_cpu(ctx->timing.beacon_interval);
/drivers/mmc/core/
H A Dcore.c981 "width %u timing %u\n",
984 ios->bus_width, ios->timing);
1499 * Select timing parameters for host.
1501 void mmc_set_timing(struct mmc_host *host, unsigned int timing) argument
1504 host->ios.timing = timing;
1546 host->ios.timing = MMC_TIMING_LEGACY;
1593 host->ios.timing = MMC_TIMING_LEGACY;
2301 host->ios.timing = MMC_TIMING_LEGACY;
/drivers/video/fbdev/
H A Dpm2fb.c238 static u32 to3264(u32 timing, int bpp, int is64) argument
242 timing *= 3;
244 timing >>= 1;
246 timing >>= 1;
251 timing >>= 1;
252 return timing;
H A Damba-clcd.c559 struct display_timing timing; local
562 err = of_get_display_timing(node, "panel-timing", &timing);
566 videomode_from_timing(&timing, &video);
/drivers/mmc/host/
H A Dsdhci-msm.c144 * timing mode) or for eMMC4.5 card read operation (in HS200
145 * timing mode).
354 !((ios.timing == MMC_TIMING_MMC_HS200) ||
355 (ios.timing == MMC_TIMING_UHS_SDR104)))
H A Drtsx_usb_sdmmc.c1070 unsigned char timing, bool *ddr_mode)
1079 switch (timing) {
1148 sd_set_timing(host, ios->timing, &host->ddr_mode);
1153 switch (ios->timing) {
1069 sd_set_timing(struct rtsx_usb_sdmmc *host, unsigned char timing, bool *ddr_mode) argument
H A Dsh_mmcif.c234 unsigned char timing; member in struct:sh_mmcif_host
812 switch (host->timing) {
815 * MMC core will only set this timing, if the host
1050 host->timing = ios->timing;
H A Dsdhci-esdhc-imx.c796 /* use average delay to get the best timing */
834 /* back to default state for other legacy timing */
841 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) argument
847 switch (timing) {
872 esdhc_change_pinstate(host, timing);
H A Dmmci.c366 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
367 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
838 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
839 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
H A Dsdhci.h408 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
H A Dusdhi6rol0.c742 if (ios->timing != MMC_TIMING_UHS_DDR50) {
816 dev_dbg(mmc_dev(mmc), "%uHz, OCR: %u, power %u, bus-width %u, timing %u\n",
817 ios->clock, ios->vdd, ios->power_mode, ios->bus_width, ios->timing);
845 if (ios->timing == MMC_TIMING_UHS_DDR50)
852 mode = ios->timing == MMC_TIMING_UHS_DDR50;
/drivers/net/wireless/rsi/
H A Drsi_91x_sdio.c183 host->ios.timing = MMC_TIMING_LEGACY;
298 host->ios.timing = MMC_TIMING_SD_HS;
/drivers/usb/
H A DKconfig131 slower than on a PCI/ISA Parallel Port, so timing critical
/drivers/net/wireless/iwlegacy/
H A Dcommon.c3652 memset(&il->timing, 0, sizeof(struct il_rxon_time_cmd));
3654 il->timing.timestamp = cpu_to_le64(il->timestamp);
3655 il->timing.listen_interval = cpu_to_le16(conf->listen_interval);
3663 il->timing.atim_win = 0;
3669 il->timing.beacon_interval = cpu_to_le16(beacon_int);
3674 il->timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
3676 il->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ? : 1) : 1;
3679 le16_to_cpu(il->timing.beacon_interval),
3680 le32_to_cpu(il->timing.beacon_init_val),
3681 le16_to_cpu(il->timing
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/drivers/media/dvb-frontends/
H A Dstv0900_sw.c1197 u8 timing; local
1201 timing = stv0900_read_reg(intp, TMGREG2);
1205 while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
1206 timing = stv0900_read_reg(intp, TMGREG2);
/drivers/nfc/
H A Dpn533.c3043 struct pn533_config_timing timing; local
3056 timing.rfu = PN533_CONFIG_TIMING_102;
3057 timing.atr_res_timeout = PN533_CONFIG_TIMING_102;
3058 timing.dep_timeout = PN533_CONFIG_TIMING_204;
3078 (u8 *)&timing, sizeof(timing));

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