Searched refs:CACHE_LINE_SIZE (Results 1 - 9 of 9) sorted by relevance

/arch/um/sys-ppc/
H A Dmisc.S22 #define CACHE_LINE_SIZE 16 define
26 #define CACHE_LINE_SIZE 32 define
39 li r0,4096/CACHE_LINE_SIZE
50 addi r3,r3,CACHE_LINE_SIZE
81 addi r11,r11,CACHE_LINE_SIZE
85 li r11,CACHE_LINE_SIZE+4
89 li r0,4096/CACHE_LINE_SIZE
97 #if CACHE_LINE_SIZE >= 32
99 #if CACHE_LINE_SIZE >= 64
102 #if CACHE_LINE_SIZE >
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/arch/m68k/coldfire/
H A Dcache.c40 : "i" (CACHE_LINE_SIZE),
/arch/arm/mm/
H A Dcache-xsc3l2.c27 #define CACHE_LINE_SIZE 32 macro
112 if (start & (CACHE_LINE_SIZE - 1)) {
113 vaddr = l2_map_va(start & ~(CACHE_LINE_SIZE - 1), vaddr);
116 start = (start | (CACHE_LINE_SIZE - 1)) + 1;
122 while (start < (end & ~(CACHE_LINE_SIZE - 1))) {
125 start += CACHE_LINE_SIZE;
148 start &= ~(CACHE_LINE_SIZE - 1);
152 start += CACHE_LINE_SIZE;
191 start &= ~(CACHE_LINE_SIZE - 1);
196 start += CACHE_LINE_SIZE;
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H A Dcache-feroceon-l2.c137 #define CACHE_LINE_SIZE 32 macro
146 BUG_ON(start & (CACHE_LINE_SIZE - 1));
147 BUG_ON(end & (CACHE_LINE_SIZE - 1));
176 if (start & (CACHE_LINE_SIZE - 1)) {
177 l2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
178 start = (start | (CACHE_LINE_SIZE - 1)) + 1;
184 if (start < end && end & (CACHE_LINE_SIZE - 1)) {
185 l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
186 end &= ~(CACHE_LINE_SIZE - 1);
194 l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE);
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H A Dcache-tauros2.c62 #define CACHE_LINE_SIZE 32 macro
69 if (start & (CACHE_LINE_SIZE - 1)) {
70 tauros2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
71 start = (start | (CACHE_LINE_SIZE - 1)) + 1;
77 if (end & (CACHE_LINE_SIZE - 1)) {
78 tauros2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
79 end &= ~(CACHE_LINE_SIZE - 1);
87 start += CACHE_LINE_SIZE;
95 start &= ~(CACHE_LINE_SIZE - 1);
98 start += CACHE_LINE_SIZE;
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H A Dcache-l2x0.c47 #define CACHE_LINE_SIZE 32 macro
235 start += CACHE_LINE_SIZE;
243 if (start & (CACHE_LINE_SIZE - 1)) {
244 start &= ~(CACHE_LINE_SIZE - 1);
246 start += CACHE_LINE_SIZE;
249 if (end & (CACHE_LINE_SIZE - 1)) {
250 end &= ~(CACHE_LINE_SIZE - 1);
262 start &= ~(CACHE_LINE_SIZE - 1);
271 start &= ~(CACHE_LINE_SIZE - 1);
353 start += CACHE_LINE_SIZE;
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H A Dcache-v6.S21 #define CACHE_LINE_SIZE 32 define
135 bic r0, r0, #CACHE_LINE_SIZE - 1
138 add r0, r0, #CACHE_LINE_SIZE
/arch/m68k/include/asm/
H A Dm53xxacr.h64 #define CACHE_LINE_SIZE 16 /* 16 byte line size */ macro
H A Dm54xxacr.h64 #define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ macro

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