Searched refs:DMA1_0_IRQ_STATUS (Results 1 - 2 of 2) sorted by relevance

/arch/blackfin/mach-bf561/include/mach/
H A DdefBF561.h324 #define DMA1_0_IRQ_STATUS 0xFFC01C28 /* DMA1 Channel 0 Interrupt/Status Register */ macro
H A DcdefBF561.h549 #define bfin_read_DMA1_0_IRQ_STATUS() bfin_read16(DMA1_0_IRQ_STATUS)
550 #define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS,val)

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