Searched refs:EPPI0_CLKDIV (Results 1 - 5 of 5) sorted by relevance

/arch/blackfin/mach-bf548/include/mach/
H A DdefBF544.h45 #define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */ macro
H A DcdefBF544.h67 #define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
68 #define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
H A DcdefBF547.h114 #define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
115 #define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
H A DdefBF547.h70 #define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */ macro
/arch/blackfin/mach-bf609/include/mach/
H A DdefBF60x_base.h1452 #define EPPI0_CLKDIV 0xFFC1801C /* EPPI0 Clock Divide Register */ macro

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