Searched refs:EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG (Results 1 - 2 of 2) sorted by relevance

/arch/arm/mach-exynos/
H A Dregs-pmu.h231 #define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG 0x11B4 macro
H A Dpmu.c256 { EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },

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