Searched refs:LO (Results 1 - 24 of 24) sorted by relevance

/arch/metag/lib/
H A Dashldi3.S22 LSR D0Ar6,D0Re0,D0Ar4 ! TMP= LO >> -(COUNT - 32)
25 LSL D0Re0,D0Re0,D0Ar4 ! LO = LO << COUNT
30 LSL D1Re0,D0Re0,D0Ar4 ! HI = LO << N
31 MOV D0Re0,#0 ! LO = 0
H A Dashrdi3.S22 LSR D0Re0,D0Re0,D0Ar4 ! LO = LO >> COUNT
24 OR D0Re0,D0Re0,D0Ar6 ! LO = LO | TMP
30 ASR D0Re0,D1Re0,D1Ar3 ! LO = HI >> N
H A Dlshrdi3.S22 LSR D0Re0,D0Re0,D0Ar4 ! LO = LO >> COUNT
24 OR D0Re0,D0Re0,D0Ar6 ! LO = LO | TMP
30 LSR D0Re0,D1Re0,D1Ar3 ! LO = HI >> N
/arch/blackfin/mach-bf609/
H A Ddpm.S13 P0.L = LO(PM_STACK);
20 P0.L = LO(DPM0_RESTORE4);
26 P0.L = LO(DPM0_CTL);
28 R3.L = LO(0x00000010);
46 P0.l = LO(SEC_SCI_BASE + SEC_CSID);
51 P1.l = LO(SEC_END);
84 P0.L = LO(PM_STACK);
96 P0.L = LO(DPM0_CTL);
98 R3.L = LO(0x00000008);
/arch/blackfin/include/asm/
H A Dtrace.h62 preg.L = LO(TBUFCTL); \
68 preg.L = LO(TBUFCTL); \
74 preg.L = LO(TBUFCTL); \
82 preg.L = LO(TBUFCTL); \
H A Dentry.h44 preg.l = LO(CHIPID); \
115 P0.L = LO(ILAT); \
145 P0.L = LO(ILAT); \
H A Dblackfin.h54 #define LO(con32) ((con32) & 0xFFFF) macro
/arch/metag/kernel/
H A Dhead.S19 ADD D0Re0,D0Re0,#LO(___pTBIs)
22 ADD D0Re0,D0Re0,#LO(___pTBISegs)
35 ADD A0StP,A0StP,#LO(_init_thread_union)
38 CALL D1RtP,#LO(_metag_start_kernel)
60 ADD A0StP,A0StP,#LO(_secondary_data_stack)
H A Dftrace_stub.S27 CALL D1RtP,#LO(_ftrace_stub)
42 ADD D0Re0,D0Re0,#LO(_ftrace_trace_function)
45 ADD D1Re0,D1Re0,#LO(_ftrace_stub)
H A Duser_gateway.S40 ADD D1Ar1,D1Ar1,#LO(USER_GATEWAY_PAGE + USER_GATEWAY_TLS)
/arch/mips/pci/
H A Dops-nile4.c11 #define LO(reg) (reg / 4) macro
41 mask = vrc_pciregs[LO(NILE4_PCIINIT1)];
42 vrc_pciregs[LO(NILE4_PCIINIT1)] = 0x0000001a | (busnum ? 0x200 : 0);
46 vrc_pciregs[LO(NILE4_PCIERR)] = 0;
68 vrc_pciregs[LO(NILE4_PCIINIT1)] = mask;
/arch/hexagon/kernel/
H A Dhead.S42 r24.L = #LO(swapper_pg_dir)
54 r1.l = #LO(PAGE_OFFSET);
75 r1.l = #LO(_end);
76 r2.l = #LO(stext);
110 R1.L = #LO(PAGE_OFFSET >> (22 - 2))
201 {r29.L = #LO(init_thread_union); r0.L = #LO(_THREAD_SIZE); }
208 { r0.L = #LO(__bss_start); r1 = #0; r2.l = #LO(__bss_stop); }
216 r0.l = #LO(__phys_offse
[all...]
H A Dvm_entry.S77 R2.L = #LO(_THREAD_SIZE); } \
229 R1.L = #LO(CHandler); \
294 R26.L = #LO(do_work_pending);
382 R26.L = #LO(do_work_pending);
/arch/metag/tbx/
H A Dtbictxfpu.S48 ADD D0Ar4, D0Ar4, #LO(METAC_CORE_ID)
54 AND D0Ar4, D0Ar4, #LO(0x0000FFFF)
64 AND D0Re0, D0Re0, #LO(TXDEFR_FPE_FE_BITS>>8)
65 AND D0Ar6, D0Ar6, #LO(TXDEFR_FPE_ICTRL_BITS)
146 AND D1Ar5, D1Ar5, #LO(TXDEFR_FPE_FE_BITS|TXDEFR_FPE_ICTRL_BITS)
151 ANDMB D1Ar5, D1Ar5, #LO(~(TXDEFR_FPE_FE_BITS|TXDEFR_FPE_ICTRL_BITS))
H A Dtbitimer.S67 CALL D0FrT,#LO(___TBITimeCore) /* and perform register update */
92 CALL D0FrT,#LO(___TBITimeCore) /* with no register update */
116 CALL D0FrT,#LO(___TBITimeCore) /* with no register update */
148 CALL D0FrT,#LO(___TBITimeCore) /* with no register update */
180 ADD A1LbP,A1LbP,#LO(___TBITimes)
H A Dtbisoft.S83 ADD D1Re0,D1Re0,#LO($LSwitchExit)
156 ADD A1LbP,A1LbP,#LO(__exit)
182 ADD A1LbP,A1LbP,#LO(__exit)
194 ADD D1RtP,D1RtP,#LO(___TBIStart)
203 ADD D1Ar1,D1Ar1,#LO($LSwitchExit)
230 ADD A1LbP,A1LbP,#LO(__exit)
H A Dtbicore.S40 ADD A1LbP,A1LbP,#LO(___pTBISegs)
58 ADD A1LbP,A1LbP,#LO(___pTBISegs)
H A Dtbiroot.S48 ADD A1LbP,A1LbP,#LO(___pTBIs)
H A Dtbipcx.S73 ADD D0FrT,D0FrT,#LO(___TBIBoingRTI+4)
86 ADD D1Ar5,D1Ar5,#LO(___TBIBoingExit)
109 ADD A0.2,A0.2,#LO($Lpcx_target)
190 ADD A1LbP,A1LbP,#LO(___pTBIs)
316 ADD D1Ar3,D1Ar3,#LO(_per_cpu__stack_save)
337 ADD D1Ar3,D1Ar3,#LO(_per_cpu__stack_save)
H A Dtbictx.S67 CALL D1RtP,#LO(___TBICtxSave)
/arch/blackfin/mach-common/
H A Dcache.S83 p0.L = LO(DSPID);
H A Dinterrupt.S167 P0.L = LO(ILAT);
188 R1.L = LO(VEC_HWERR);
200 p0.l = LO(EBIU_ERRMST);
H A Dentry.S367 P4.L = LO(IMEM_CONTROL);
376 P4.L = LO(DMEM_CONTROL);
780 r2 = LO(~0x37) (Z);
891 r1 = LO(~0x8000) (Z);
1194 P4.L = LO(IMEM_CONTROL);
1203 P4.L = LO(DMEM_CONTROL);
/arch/hexagon/lib/
H A Dmemcpy.S222 mask.l = #LO(0x7fffffff);
235 r31.l = #LO(.Lmemcpy_return); /* set up final return pointer */

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