Searched refs:MDMA_D1_CONFIG (Results 1 - 14 of 14) sorted by relevance

/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h357 #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
358 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
H A DdefBF532.h298 #define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */ macro
/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF512.h755 #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
756 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
H A DdefBF512.h419 #define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ macro
/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF522.h772 #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
773 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
H A DdefBF522.h419 #define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ macro
/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h395 #define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ macro
H A DcdefBF534.h734 #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
735 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
/arch/blackfin/mach-bf561/include/mach/
H A DdefBF561.h510 #define MDMA_D1_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */ macro
H A DcdefBF561.h1310 #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
1311 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
/arch/blackfin/mach-bf538/include/mach/
H A DdefBF538.h340 #define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA0 Stream 1 Destination Configuration Register */ macro
H A DcdefBF538.h1066 #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
1067 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h430 #define MDMA_D1_CONFIG 0xffc00f88 /* Memory DMA Stream 1 Destination Configuration Register */ macro
H A DcdefBF54x_base.h716 #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
717 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)

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