Searched refs:PTRS_PER_PMD (Results 1 - 25 of 78) sorted by relevance

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/arch/x86/include/asm/
H A Dpgtable-3level_types.h40 #define PTRS_PER_PMD 512 macro
H A Dpgtable_64_types.h42 #define PTRS_PER_PMD 512 macro
/arch/powerpc/include/asm/
H A Dpgtable-ppc64-64k.h19 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) macro
H A Dpgtable-ppc64-4k.h21 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) macro
/arch/sh/include/asm/
H A Dpgtable-3level.h25 #define PTRS_PER_PMD ((1 << PGDIR_SHIFT) / PMD_SIZE) macro
39 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
/arch/m68k/include/asm/
H A Dpgtable_mm.h57 #define PTRS_PER_PMD 1 macro
61 #define PTRS_PER_PMD 1 macro
65 #define PTRS_PER_PMD 8 macro
/arch/frv/mm/
H A Dpgalloc.c113 if (PTRS_PER_PMD == 1)
120 if (PTRS_PER_PMD > 1)
128 /* never called when PTRS_PER_PMD > 1 */
/arch/um/include/asm/
H A Dpgtable-3level.h36 #define PTRS_PER_PMD 512 macro
39 #define PTRS_PER_PMD 1024 macro
/arch/mips/include/asm/
H A Dpgtable-64.h29 * single 4K page, giving 512 (== PTRS_PER_PMD) 8 byte pointers to page
113 #define PTRS_PER_PMD ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t)) macro
132 min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \
165 extern pmd_t invalid_pmd_table[PTRS_PER_PMD];
244 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
/arch/sh/mm/
H A Dpgtable.c27 PTRS_PER_PMD * (1<<PTE_MAGNITUDE),
/arch/mn10300/mm/
H A Dpgtable.c132 if (PTRS_PER_PMD == 1)
139 if (PTRS_PER_PMD > 1)
147 /* never called when PTRS_PER_PMD > 1 */
/arch/x86/kernel/
H A Dhead64.c35 extern pmd_t early_dynamic_pgts[EARLY_DYNAMIC_PAGE_TABLES][PTRS_PER_PMD];
99 for (i = 0; i < PTRS_PER_PMD; i++)
/arch/m32r/include/asm/
H A Dpgtable-2level.h17 #define PTRS_PER_PMD 1 macro
/arch/mips/mm/
H A Dpgtable-64.c49 end = p + PTRS_PER_PMD;
/arch/unicore32/kernel/
H A Dhibernate.c93 for (pmd_idx = 0; pmd_idx < PTRS_PER_PMD; pmd++, pmd_idx++) {
/arch/x86/mm/
H A Ddump_pagetables.c97 #define PUD_LEVEL_MULT (PTRS_PER_PMD * PMD_LEVEL_MULT)
282 #if PTRS_PER_PMD > 1
291 for (i = 0; i < PTRS_PER_PMD; i++) {
/arch/arm/include/asm/
H A Dkvm_mmu.h93 clean_dcache_area(pmd, PTRS_PER_PMD * sizeof(pmd_t));
H A Dpgtable-2level.h72 #define PTRS_PER_PMD 1 macro
H A Dpgtable-3level.h33 #define PTRS_PER_PMD 512 macro
169 #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
/arch/arm/mm/
H A Didmap.c39 PTRS_PER_PMD * sizeof(pmd_t));
/arch/tile/include/asm/
H A Dpgtable_64.h29 * of PTRS_PER_PMD pgd_t's and is the middle level of the page table.
34 #define PTRS_PER_PMD _HV_L1_ENTRIES(HPAGE_SHIFT) macro
/arch/x86/power/
H A Dhibernate_32.c101 for (pmd_idx = 0; pmd_idx < PTRS_PER_PMD; pmd++, pmd_idx++) {
/arch/parisc/mm/
H A Dinit.c43 pmd_t pmd0[PTRS_PER_PMD] __attribute__ ((__section__ (".data..vm0.pmd"), aligned(PAGE_SIZE)));
424 #if PTRS_PER_PMD == 1
427 start_pmd = ((start_vaddr >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
434 #if PTRS_PER_PMD == 1
455 for (tmp1 = start_pmd; tmp1 < PTRS_PER_PMD; tmp1++, pmd++) {
779 #if PTRS_PER_PMD == 1
782 start_pmd = ((hpux_gw_page_addr >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
787 #if PTRS_PER_PMD == 1
/arch/tile/kernel/
H A Dhead_64.S246 .rept PTRS_PER_PMD
261 .rept PTRS_PER_PMD
/arch/arm64/include/asm/
H A Dkvm_mmu.h183 (pmd_t *)hwpgd + i * PTRS_PER_PMD);

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