Searched refs:PTRS_PER_PTE (Results 1 - 25 of 98) sorted by relevance

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/arch/x86/include/asm/
H A Dpgtable-2level_types.h35 #define PTRS_PER_PTE 1024 macro
H A Dpgtable-3level_types.h45 #define PTRS_PER_PTE 512 macro
H A Dpgtable_64_types.h47 #define PTRS_PER_PTE 512 macro
/arch/powerpc/include/asm/
H A Dpgtable-ppc64-64k.h18 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) macro
H A Dpgtable-ppc64-4k.h20 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) macro
/arch/tile/include/asm/
H A Dpgtable_32.h33 * PTRS_PER_PTE pte_t's and is the bottom level of the page table.
37 #define PTRS_PER_PTE _HV_L2_ENTRIES(HPAGE_SHIFT, PAGE_SHIFT) macro
53 #define LAST_PKMAP PTRS_PER_PTE
/arch/arm/include/asm/
H A Dpgtable-2level.h71 #define PTRS_PER_PTE 512 macro
75 #define PTE_HWTABLE_PTRS (PTRS_PER_PTE)
77 #define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u32))
H A Dhighmem.h7 #define LAST_PKMAP PTRS_PER_PTE
/arch/m68k/include/asm/
H A Dpgtable_mm.h56 #define PTRS_PER_PTE 16 macro
60 #define PTRS_PER_PTE 512 macro
64 #define PTRS_PER_PTE 1024 macro
/arch/avr32/include/asm/
H A Dpgtable-2level.h19 #define PTRS_PER_PTE 1024 macro
/arch/hexagon/include/asm/
H A Dmem-layout.h97 #define LAST_PKMAP PTRS_PER_PTE
H A Dpgtable.h99 #define PTRS_PER_PTE 1024 macro
103 #define PTRS_PER_PTE 256 macro
107 #define PTRS_PER_PTE 64 macro
111 #define PTRS_PER_PTE 16 macro
115 #define PTRS_PER_PTE 4 macro
453 #define __pte_offset(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
/arch/metag/include/asm/
H A Dhighmem.h27 #define LAST_PKMAP PTRS_PER_PTE
/arch/um/include/asm/
H A Dpgtable-2level.h23 #define PTRS_PER_PTE 1024 macro
/arch/arc/include/asm/
H A Dpgalloc.h90 return get_order(PTRS_PER_PTE * 4);
113 memzero((void *)pte_pg, PTRS_PER_PTE * 4);
/arch/m68k/mm/
H A Dsun3mmu.c68 next_pgtable += PTRS_PER_PTE * sizeof (pte_t);
74 for (i=0; i<PTRS_PER_PTE; ++i, ++pg_table) {
/arch/unicore32/include/asm/
H A Dpgalloc.h43 clean_dcache_area(pte, PTRS_PER_PTE * sizeof(pte_t));
58 clean_dcache_area(page, PTRS_PER_PTE * sizeof(pte_t));
/arch/xtensa/mm/
H A Dmmu.c28 n_pages = ALIGN(n_pages, PTRS_PER_PTE);
38 for (i = 0; i < n_pages; i += PTRS_PER_PTE, ++pmd) {
/arch/mips/include/asm/
H A Dpgtable-64.h31 * PTRS_PER_PTE) 8 byte ptes. Each pud entry is initialized to point to
115 #define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) macro
132 min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \
151 extern pte_t invalid_pte_table[PTRS_PER_PTE];
152 extern pte_t empty_bad_page_table[PTRS_PER_PTE];
266 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
/arch/arm64/include/asm/
H A Dpgtable-hwdef.h19 #define PTRS_PER_PTE (1 << (PAGE_SHIFT - 3)) macro
28 #define PTRS_PER_PMD PTRS_PER_PTE
38 #define PTRS_PER_PUD PTRS_PER_PTE
/arch/mn10300/mm/
H A Dinit.c61 for (loop = VMALLOC_START / (PAGE_SIZE * PTRS_PER_PTE);
62 loop < VMALLOC_END / (PAGE_SIZE * PTRS_PER_PTE);
/arch/x86/power/
H A Dhibernate_32.c111 pfn += PTRS_PER_PTE;
119 max_pte = pte + PTRS_PER_PTE;
/arch/powerpc/mm/
H A Dsubpage-prot.c120 i = (addr >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
121 nw = PTRS_PER_PTE - i;
247 i = (addr >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
248 nw = PTRS_PER_PTE - i;
/arch/score/mm/
H A Dinit.c109 pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned(PTE_ORDER);
/arch/xtensa/include/asm/
H A Dhighmem.h23 #define LAST_PKMAP (PTRS_PER_PTE * DCACHE_N_COLORS)

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