Searched refs:R6 (Results 1 - 23 of 23) sorted by relevance

/arch/blackfin/lib/
H A Dmodsi3.S39 [--SP] = (R7:6); /* Push R7 and R6 */
42 R6 = R1; /* Save for later */ define
46 R0 *= R6; /* Quotient * divisor */
H A Dumodsi3.S35 R6 = R1; define
39 R0 *= R6; /* Quotient * divisor */
H A Ddivsi3.S115 R6 = R0 ^ R1; /* Get sign */ define
116 R5 = R6 >> 31; /* Shift sign to LSB */
120 R6 = R0 ^ R1; /* Get new quotient bit */ define
127 CC = R6 < 0; /* Check quotient(AQ) */
131 R6 = R0 ^ R1; /* Generate next quotient bit */ define
132 R5 = R6 >> 31;
144 (R7:5)= [SP++]; /* Pop registers R6-R7 */
H A Dudivsi3.S121 R6 = 2; /* assume we'll shift two */ define
131 IF !CC R6 = R3; /* R1 doesn't, so at most 1 shifted */
139 IF CC P0 = R6; /* Number of values divided */
150 .Lulst: R6 = R2 >> 31; /* R6 = sign bit of R2, for carry */
153 R3 = R3 | R6; /* Include any carry */
166 R6 = R2 << 1; define
168 IF CC R2 = R6; /* if 1, Q = Q*2 */
175 R6 = CC; /* if yes, R6 define
[all...]
/arch/x86/crypto/
H A Daes-x86_64-asm_64.S43 #define R6 %rdi define
134 prologue(FUNC,KEY,B128,B192,R2,R8,R7,R9,R1,R3,R4,R6,R10,R5,R11)
136 #define return(FUNC) epilogue(FUNC,R8,R2,R9,R7,R5,R6,R3,R4,R11)
139 round(TAB,OFFSET,R1,R2,R3,R4,R5,R6,R7,R10,R5,R6,R3,R4) \
140 move_regs(R1,R2,R5,R6)
143 round(TAB,OFFSET,R1,R2,R3,R4,R5,R6,R7,R10,R5,R6,R3,R4)
146 round(TAB,OFFSET,R2,R1,R4,R3,R6,R5,R7,R10,R5,R6,R
[all...]
/arch/powerpc/mm/
H A Dhash_low_64.S59 std r6,STK_PARAM(R6)(r1)
266 ld r6,STK_PARAM(R6)(r1)
325 ld r6,STK_PARAM(R6)(r1)
353 std r6,STK_PARAM(R6)(r1)
505 ld r6,STK_PARAM(R6)(r1)
613 ld r6,STK_PARAM(R6)(r1)
683 ld r6,STK_PARAM(R6)(r1)
696 ld r6,STK_PARAM(R6)(r1)
716 std r6,STK_PARAM(R6)(r1)
930 ld r6,STK_PARAM(R6)(r
[all...]
H A Dtlb_nohash_low.S223 PPC_ICBT(0,R6,R7) /* touch next cache line */
225 PPC_ICBT(0,R6,R7) /* touch next cache line */
227 PPC_ICBT(0,R6,R7) /* touch next cache line */
/arch/blackfin/mach-common/
H A Dentry.S60 R6 = VEC_CPLB_M; /* Data CPLB Miss */ define
61 cc = R6 == R7;
64 R6 = VEC_CPLB_VL; /* Data CPLB Violation */ define
65 cc = R6 == R7;
112 CC = R7 == R6;
222 cc = R7 == R6;
249 CC = R7 == R6;
1137 R6 = ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN)*1024) - 1; define
1142 R7 = R7 & R6;
1158 R7 = R7 & R6;
[all...]
H A Ddpmc_modes.S108 R6 = W[P0](z); define
173 W[P0]= R6; /* Restore CCLK and SCLK divider */
/arch/m32r/kernel/
H A Dentry.S85 #define R6(reg) @(0x08,reg) define
257 ld r6, R6(sp)
/arch/powerpc/platforms/pseries/
H A DhvCall.S40 std r6,STK_PARAM(R6)(r1); \
52 ld r6,STACK_FRAME_OVERHEAD+STK_PARAM(R6)(r1); \
/arch/ia64/kernel/
H A Dentry.h55 .spillsp r6,SW(R6)+16+(off); .spillsp r7,SW(R7)+16+(off); \
H A Dentry.S269 st8.spill [r14]=r4,SW(R6)-SW(R4) // spill r4 and prefetch offset 0x1c0
284 st8.spill [r14]=r6,SW(B0)-SW(R6) // spill r6
/arch/powerpc/kernel/
H A Dfpu.S219 SAVE_32FPVSRS(0, R4, R6)
H A Dtm.S166 SAVE_32FPRS_VSRS(0, R6, R7) /* r6 scratch, r7 transact fp state */
/arch/powerpc/kvm/
H A Dbookehv_interrupts.S188 PPC_STL r6, VCPU_GPR(R6)(r4)
299 PPC_STL r6, VCPU_GPR(R6)(r11)
326 PPC_STL r6, VCPU_GPR(R6)(r11)
682 PPC_LL r6, VCPU_GPR(R6)(r4)
H A Dbooke_interrupts.S63 stw r6, VCPU_GPR(R6)(r4)
488 lwz r6, VCPU_GPR(R6)(r4)
H A Dbook3s_hv_rmhandlers.S1005 ld r6, VCPU_GPR(R6)(r4)
1065 std r6, VCPU_GPR(R6)(r9)
/arch/cris/arch-v10/kernel/
H A Dkgdb.c303 R4, R5, R6, R7, enumerator in enum:register_name
951 " move.d $r6,[cris_reg+0x18] ; Save R6\n"
1004 " move.d [cris_reg+0x18],$r6 ; Restore R6\n"
1047 " move.d $r6,[cris_reg+0x18] ; Save R6\n"
1102 " move.d [cris_reg+0x18],$r6 ; Restore R6\n"
/arch/cris/arch-v32/kernel/
H A Dkgdb_asm.S41 move.d $r6, [$acr] ; Save R6
483 move.d [$acr], $r6 ; Restore R6
H A Dkgdb.c312 R4, R5, R6, R7, enumerator in enum:register_name
/arch/hexagon/lib/
H A Dmemcpy.S160 #define data0 R6 /* lower 8 bytes of ldata0 */
/arch/blackfin/include/asm/
H A Ddpmc.h14 #define PM_REG1 R6

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