Searched refs:REG2 (Results 1 - 6 of 6) sorted by relevance
| /arch/sparc/include/asm/ |
| H A D | tsb.h | 98 #define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \
99 661: casa [TSB] ASI_N, REG1, REG2; \
102 casa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
105 #define TSB_CAS_TAG(TSB, REG1, REG2) \
106 661: casxa [TSB] ASI_N, REG1, REG2; \
109 casxa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
119 #define TSB_LOCK_TAG(TSB, REG1, REG2) \
121 sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\
122 andcc REG1, REG2, %g0; \
125 TSB_CAS_TAG_HIGH(TSB, REG1, REG2); \
[all...] |
| H A D | trap_block.h | 166 * area base of the current processor into DEST. REG1, REG2, and REG3 are
174 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \
176 sethi %hi(trap_block), REG2; \
178 or REG2, %lo(trap_block), REG2; \
179 add REG2, REG1, REG2; \
180 ldx [REG2 + TRAP_PER_CPU_PER_CPU_BASE], DEST;
203 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
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| /arch/m32r/kernel/ |
| H A D | align.c | 39 #define REG2(insn) ((insn) & 0x000f) macro
106 int src = REG2(insn);
124 val += (unsigned int)get_reg(regs, REG2(insn));
142 val &= get_reg(regs, REG2(insn));
150 if (get_reg(regs, REG1(insn)) < get_reg(regs, REG2(insn)))
160 if (get_reg(regs, REG1(insn)) == get_reg(regs, REG2(insn)))
171 < (unsigned int)get_reg(regs, REG2(insn)))
181 if (!get_reg(regs, REG2(insn)))
193 val = get_reg(regs, REG2(insn));
203 val = get_reg(regs, REG2(ins
[all...] |
| /arch/sparc/kernel/ |
| H A D | sys32.S | 22 #define SIGN2(STUB,SYSCALL,REG1,REG2) \
28 sra REG2, 0, REG2
30 #define SIGN3(STUB,SYSCALL,REG1,REG2,REG3) \
35 sra REG2, 0, REG2; \
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| /arch/arm/boot/dts/ |
| H A D | rk3288-evb-act8846.dts | 48 vcc_io: REG2 {
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| H A D | rk3188-radxarock.dts | 152 vdd_log: REG2 {
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