Searched refs:SDRC_RFR_CTRL_133MHz (Results 1 - 3 of 3) sorted by relevance

/arch/arm/mach-omap2/
H A Dopp2420_data.c80 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
86 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
106 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
112 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
H A Dopp2430_data.c59 SDRC_RFR_CTRL_133MHz,
75 SDRC_RFR_CTRL_133MHz,
91 SDRC_RFR_CTRL_133MHz,
107 SDRC_RFR_CTRL_133MHz,
H A Dsdrc.h189 #define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1) macro

Completed in 19 milliseconds