Searched refs:SET (Results 1 - 12 of 12) sorted by relevance

/arch/arm/mach-imx/
H A Dclk-pfd.c28 * register has SET, CLR and TOG registers at offset 0x4 0x8 and 0xc.
38 #define SET 0x4 macro
55 writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET);
107 writel_relaxed(frac << (pfd->idx * 8), pfd->reg + SET);
/arch/metag/tbx/
H A Dtbicore.S105 * !!On return Zero flag is SET if we are sucessfull!!
118 SET [A0.3+#UON],D1RtP /* Stop shared memory access too */
126 SET [A0.3+#UOFF],D1RtP /* Allow shared memory access */
/arch/arm/boot/compressed/
H A Dhead-sharpsl.S130 bic r3, r3, #0x11 @ SET NCE
131 orr r3, r3, #0x0a @ SET CLR + FLWP
136 orr r3, r3, #4 @ SET ALE
/arch/mips/mm/
H A Duasm-mips.c71 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
72 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
98 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
101 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
195 if (ip->fields & SET)
H A Duasm-micromips.c202 if (ip->fields & SET)
H A Duasm.c26 SET = 0x200, enumerator in enum:fields
/arch/c6x/kernel/
H A Dentry.S38 SET .S2 reg,0,0,reg
249 SET .S2 B1,0,0,B1
/arch/m68k/fpsp040/
H A Dssin.S170 |--SET ADJN TO 0
176 |--SET ADJN TO 1
533 |--SET ADJN TO 4
H A Dsatan.S274 |--SIXTH BITS IS SET TO BE 1. SINCE K = -4, -3, ..., 3, THERE
282 oril #0x04000000,XFRAC(%a6) | ...SET 6-TH BIT TO 1
/arch/blackfin/kernel/
H A Ddebug-mmrs.c364 __PORT(SET, data_set);
373 __PORT(SET, data_set);
/arch/m68k/ifpsp060/src/
H A Dfplsp.S5016 mov.l &0,ADJN(%a6) # yes; SET ADJN TO 0
5022 mov.l &1,ADJN(%a6) # yes; SET ADJN TO 1
5236 #--SET ADJN TO 4
6275 #--SIXTH BITS IS SET TO BE 1. SINCE K = -4, -3, ..., 3, THERE
6282 or.l &0x04000000,XFRAC(%a6) # SET 6-TH BIT TO 1
H A Dfpsp.S5122 mov.l &0,ADJN(%a6) # yes; SET ADJN TO 0
5128 mov.l &1,ADJN(%a6) # yes; SET ADJN TO 1
5342 #--SET ADJN TO 4
6381 #--SIXTH BITS IS SET TO BE 1. SINCE K = -4, -3, ..., 3, THERE
6388 or.l &0x04000000,XFRAC(%a6) # SET 6-TH BIT TO 1

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