Searched refs:SICB_IWR1 (Results 1 - 4 of 4) sorted by relevance

/arch/blackfin/mach-bf561/
H A Dsecondary.S149 [P0 + (SICB_IWR1 - SYSMMR_BASE)] = R0;
/arch/blackfin/mach-bf561/include/mach/
H A DdefBF561.h65 #define SICB_IWR1 0xFFC01120 /* SIC Interrupt Wakeup-Enable register 1 */ macro
H A DcdefBF561.h94 #define bfin_read_SICB_IWR1() bfin_read32(SICB_IWR1)
95 #define bfin_write_SICB_IWR1(val) bfin_write32(SICB_IWR1,val)
/arch/blackfin/kernel/
H A Ddebug-mmrs.c1518 D32(SICB_IWR1);

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