Searched refs:counter (Results 1 - 25 of 135) sorted by relevance

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/arch/x86/kernel/cpu/
H A Dperfctr-watchdog.c46 /* returns the bit offset of the performance counter register */
98 int avail_to_resrv_perfctr_nmi_bit(unsigned int counter) argument
100 BUG_ON(counter > NMI_MAX_COUNTER_BITS);
102 return !test_bit(counter, perfctr_nmi_owner);
108 unsigned int counter; local
110 counter = nmi_perfctr_msr_to_bit(msr);
112 if (counter > NMI_MAX_COUNTER_BITS)
115 if (!test_and_set_bit(counter, perfctr_nmi_owner))
123 unsigned int counter; local
125 counter
136 unsigned int counter; local
151 unsigned int counter; local
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/arch/arc/include/asm/
H A Dspinlock_types.h28 volatile unsigned int counter; member in struct:__anon133
33 #define __ARCH_RW_LOCK_UNLOCKED { .counter = __ARCH_RW_LOCK_UNLOCKED__ }
H A Dspinlock.h62 * The spinlock itself is contained in @counter and access to it is
69 #define arch_read_can_lock(x) ((x)->counter > 0)
72 #define arch_write_can_lock(x) ((x)->counter == __ARCH_RW_LOCK_UNLOCKED__)
85 if (rw->counter > 0) {
86 rw->counter--;
109 if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) {
110 rw->counter = 0;
133 rw->counter++;
140 rw->counter = __ARCH_RW_LOCK_UNLOCKED__;
/arch/x86/include/asm/
H A Datomic64_64.h21 return ACCESS_ONCE((v)->counter);
33 v->counter = i;
46 : "=m" (v->counter)
47 : "er" (i), "m" (v->counter));
60 : "=m" (v->counter)
61 : "er" (i), "m" (v->counter));
75 GEN_BINARY_RMWcc(LOCK_PREFIX "subq", v->counter, "er", i, "%0", "e");
87 : "=m" (v->counter)
88 : "m" (v->counter));
100 : "=m" (v->counter)
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H A Datomic.h27 return ACCESS_ONCE((v)->counter);
39 v->counter = i;
52 : "+m" (v->counter)
66 : "+m" (v->counter)
81 GEN_BINARY_RMWcc(LOCK_PREFIX "subl", v->counter, "er", i, "%0", "e");
93 : "+m" (v->counter));
105 : "+m" (v->counter));
118 GEN_UNARY_RMWcc(LOCK_PREFIX "decl", v->counter, "%0", "e");
131 GEN_UNARY_RMWcc(LOCK_PREFIX "incl", v->counter, "%0", "e");
145 GEN_BINARY_RMWcc(LOCK_PREFIX "addl", v->counter, "e
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H A Dlocal.h21 : "+m" (l->a.counter));
27 : "+m" (l->a.counter));
33 : "+m" (l->a.counter)
40 : "+m" (l->a.counter)
55 GEN_BINARY_RMWcc(_ASM_SUB, l->a.counter, "er", i, "%0", "e");
68 GEN_UNARY_RMWcc(_ASM_DEC, l->a.counter, "%0", "e");
81 GEN_UNARY_RMWcc(_ASM_INC, l->a.counter, "%0", "e");
95 GEN_BINARY_RMWcc(_ASM_ADD, l->a.counter, "er", i, "%0", "s");
109 : "+r" (i), "+m" (l->a.counter)
123 (cmpxchg_local(&((l)->a.counter), (
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/arch/arm/include/asm/
H A Datomic.h30 #define atomic_read(v) ACCESS_ONCE((v)->counter)
31 #define atomic_set(v,i) (((v)->counter) = (i))
47 prefetchw(&v->counter); \
54 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
55 : "r" (&v->counter), "Ir" (i) \
66 prefetchw(&v->counter); \
74 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
75 : "r" (&v->counter), "Ir" (i) \
89 prefetchw(&ptr->counter);
97 : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
216 long long counter; member in struct:__anon144
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/arch/parisc/include/asm/
H A Dspinlock_types.h16 volatile int counter; member in struct:__anon2276
H A Dspinlock.h64 * In the PA-RISC implementation, we have a spinlock and a counter.
65 * Readers use the lock to serialise their access to the counter (which
78 rw->counter++;
90 rw->counter--;
103 rw->counter++;
111 if (rw->counter < 0)
115 while (arch_spin_is_locked(&rw->lock) && rw->counter >= 0)
130 if (rw->counter != 0) {
134 while (rw->counter != 0)
140 rw->counter
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/arch/microblaze/include/asm/
H A Datomic.h18 res = v->counter - 1;
20 v->counter = res;
H A Dmodule.h29 typedef struct { volatile int counter; } module_t; member in struct:__anon1939
/arch/powerpc/include/asm/
H A Datomic.h19 __asm__ __volatile__("lwz%U1%X1 %0,%1" : "=r"(t) : "m"(v->counter));
26 __asm__ __volatile__("stw%U0%X0 %1,%0" : "=m"(v->counter) : "r"(i));
40 : "=&r" (t), "+m" (v->counter) \
41 : "r" (a), "r" (&v->counter) \
59 : "r" (a), "r" (&v->counter) \
86 : "=&r" (t), "+m" (v->counter)
87 : "r" (&v->counter)
104 : "r" (&v->counter)
130 : "=&r" (t), "+m" (v->counter)
131 : "r" (&v->counter)
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H A Dlocal.h33 : "r" (a), "r" (&(l->a.counter))
52 : "r" (a), "r" (&(l->a.counter))
69 : "r" (&(l->a.counter))
96 : "r" (&(l->a.counter))
103 (cmpxchg_local(&((l)->a.counter), (o), (n)))
104 #define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n)))
130 : "r" (&(l->a.counter)), "r" (a), "r" (u)
159 : "r" (&(l->a.counter))
170 #define __local_inc(l) ((l)->a.counter++)
171 #define __local_dec(l) ((l)->a.counter
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/arch/metag/include/asm/
H A Datomic_lock1.h13 return (v)->counter;
18 * possible race, as it reads the counter twice:
22 * ret = v->counter (non-zero)
23 * if (ret != u) v->counter = 0
24 * v->counter += 1 (counter set to 1)
35 v->counter = i;
47 v->counter c_op i; \
58 result = v->counter; \
61 v->counter
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H A Datomic_lnkget.h6 #define atomic_set(v, i) ((v)->counter = (i))
25 : "da" (&v->counter));
44 : "da" (&v->counter), "bd" (i) \
64 : "da" (&v->counter), "bd" (i) \
94 : "da" (&v->counter), "bd" (~mask)
111 : "da" (&v->counter), "bd" (mask)
132 : "da" (&v->counter), "bd" (old), "da" (new)
152 : "da" (&v->counter), "da" (new)
176 : "da" (&v->counter), "bd" (u), "bd" (a)
199 : "da" (&v->counter), "b
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/arch/blackfin/include/asm/
H A Datomic.h25 #define atomic_read(v) __raw_uncached_fetch_asm(&(v)->counter)
27 #define atomic_add_return(i, v) __raw_atomic_update_asm(&(v)->counter, i)
28 #define atomic_sub_return(i, v) __raw_atomic_update_asm(&(v)->counter, -(i))
30 #define atomic_clear_mask(m, v) __raw_atomic_clear_asm(&(v)->counter, m)
31 #define atomic_set_mask(m, v) __raw_atomic_set_asm(&(v)->counter, m)
/arch/avr32/include/asm/
H A Datomic.h22 #define atomic_read(v) ACCESS_ONCE((v)->counter)
23 #define atomic_set(v, i) (((v)->counter) = i)
37 : "=&r" (result), "=o" (v->counter) \
38 : "m" (v->counter), #asm_con (i) \
117 : "=&r"(tmp), "=o"(v->counter)
118 : "m"(v->counter), "rKs21"(-a), "rKs21"(u)
131 : "=&r"(tmp), "=o"(v->counter)
132 : "m"(v->counter), "r"(a), "ir"(u)
162 : "=&r"(result), "=o"(v->counter)
163 : "m"(v->counter), "i
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/arch/mips/include/asm/
H A Dlocal.h43 : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
44 : "Ir" (i), "m" (l->a.counter)
57 : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
58 : "Ir" (i), "m" (l->a.counter)
64 result = l->a.counter;
66 l->a.counter = result;
88 : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
89 : "Ir" (i), "m" (l->a.counter)
102 : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
103 : "Ir" (i), "m" (l->a.counter)
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H A Datomic.h32 #define atomic_read(v) ACCESS_ONCE((v)->counter)
41 #define atomic_set(v, i) ((v)->counter = (i))
56 : "=&r" (temp), "+m" (v->counter) \
68 : "=&r" (temp), "+m" (v->counter) \
75 v->counter c_op i; \
98 : "=&r" (result), "=&r" (temp), "+m" (v->counter) \
110 : "=&r" (result), "=&r" (temp), "+m" (v->counter) \
119 result = v->counter; \
121 v->counter = result; \
170 : "=&r" (result), "=&r" (temp), "+m" (v->counter)
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/arch/alpha/include/asm/
H A Datomic.h20 #define atomic_read(v) ACCESS_ONCE((v)->counter)
21 #define atomic64_read(v) ACCESS_ONCE((v)->counter)
23 #define atomic_set(v,i) ((v)->counter = (i))
24 #define atomic64_set(v,i) ((v)->counter = (i))
44 :"=&r" (temp), "=m" (v->counter) \
45 :"Ir" (i), "m" (v->counter)); \
62 :"=&r" (temp), "=m" (v->counter), "=&r" (result) \
63 :"Ir" (i), "m" (v->counter) : "memory"); \
80 :"=&r" (temp), "=m" (v->counter) \
81 :"Ir" (i), "m" (v->counter)); \
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H A Dlocal.h32 :"=&r" (temp), "=m" (l->a.counter), "=&r" (result)
33 :"Ir" (i), "m" (l->a.counter) : "memory");
49 :"=&r" (temp), "=m" (l->a.counter), "=&r" (result)
50 :"Ir" (i), "m" (l->a.counter) : "memory");
55 (cmpxchg_local(&((l)->a.counter), (o), (n)))
56 #define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n)))
96 #define __local_inc(l) ((l)->a.counter++)
97 #define __local_dec(l) ((l)->a.counter++)
98 #define __local_add(i,l) ((l)->a.counter+=(i))
99 #define __local_sub(i,l) ((l)->a.counter
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/arch/cris/include/asm/
H A Datomic.h20 #define atomic_read(v) ACCESS_ONCE((v)->counter)
21 #define atomic_set(v,i) (((v)->counter) = (i))
30 v->counter c_op i; \
40 retval = (v->counter c_op i); \
61 retval = (v->counter -= i) == 0;
70 (v->counter)++;
78 (v->counter)--;
87 retval = ++(v->counter);
97 retval = --(v->counter);
106 retval = --(v->counter)
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/arch/sh/include/asm/
H A Datomic-llsc.h29 : "r" (i), "r" (&v->counter) \
45 : "r" (i), "r" (&v->counter) \
70 : "r" (~mask), "r" (&v->counter)
84 : "r" (mask), "r" (&v->counter)
H A Dmutex-llsc.h32 : "r" (&(count)->counter)
50 : "r" (&(count)->counter)
70 : "r" (&(count)->counter)
104 : "r" (&count->counter)
/arch/tile/include/asm/
H A Datomic_64.h27 #define atomic_set(v, i) ((v)->counter = (i))
37 __insn_fetchadd4((void *)&v->counter, i);
44 val = __insn_fetchadd4((void *)&v->counter, i) + i;
51 int guess, oldval = v->counter;
56 oldval = cmpxchg(&v->counter, guess, guess + a);
65 #define atomic64_read(v) ((v)->counter)
66 #define atomic64_set(v, i) ((v)->counter = (i))
70 __insn_fetchadd((void *)&v->counter, i);
77 val = __insn_fetchadd((void *)&v->counter, i) + i;
84 long guess, oldval = v->counter;
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