Searched refs:csr (Results 1 - 25 of 44) sorted by relevance

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/arch/sh/kernel/cpu/
H A Dadc.c15 unsigned char csr; local
21 csr = __raw_readb(ADCSR);
22 csr = channel | ADCSR_ADST | ADCSR_CKS;
23 __raw_writeb(csr, ADCSR);
26 csr = __raw_readb(ADCSR);
27 } while ((csr & ADCSR_ADF) == 0);
29 csr &= ~(ADCSR_ADF | ADCSR_ADST);
30 __raw_writeb(csr, ADCSR);
/arch/sparc/kernel/
H A Debus.c73 u32 csr = 0; local
76 csr = readl(p->regs + EBDMA_CSR);
77 writel(csr, p->regs + EBDMA_CSR);
80 if (csr & EBDMA_CSR_ERR_PEND) {
84 } else if (csr & EBDMA_CSR_INT_PEND) {
86 (csr & EBDMA_CSR_TC) ?
98 u32 csr; local
112 csr = EBDMA_CSR_BURST_SZ_16 | EBDMA_CSR_EN_CNT;
115 csr |= EBDMA_CSR_TCI_DIS;
117 writel(csr,
126 u32 csr; local
158 u32 csr; local
178 u32 csr; local
207 u32 csr; local
243 u32 orig_csr, csr; local
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/arch/alpha/kernel/
H A Dcore_tsunami.c181 volatile unsigned long *csr;
186 csr = &pchip->tlbia.csr;
188 csr = &pchip->tlbiv.csr;
194 *csr = value;
196 *csr;
228 TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */
232 if (TSUNAMI_cchip->misc.csr & (1L << 28)) {
233 int source = (TSUNAMI_cchip->misc.csr >> 2
180 volatile unsigned long *csr; local
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H A Dcore_wildfire.c118 pci->pci_window[0].wbase.csr = hose->sg_isa->dma_base | 3;
119 pci->pci_window[0].wmask.csr = (hose->sg_isa->size - 1) & 0xfff00000;
120 pci->pci_window[0].tbase.csr = virt_to_phys(hose->sg_isa->ptes);
122 pci->pci_window[1].wbase.csr = 0x40000000 | 1;
123 pci->pci_window[1].wmask.csr = (0x40000000 -1) & 0xfff00000;
124 pci->pci_window[1].tbase.csr = 0;
126 pci->pci_window[2].wbase.csr = 0x80000000 | 1;
127 pci->pci_window[2].wmask.csr = (0x40000000 -1) & 0xfff00000;
128 pci->pci_window[2].tbase.csr = 0x40000000;
130 pci->pci_window[3].wbase.csr
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H A Dcore_titan.c210 volatile unsigned long *csr;
223 csr = &port->port_specific.g.gtlbia.csr;
225 csr = &port->port_specific.g.gtlbiv.csr;
232 *csr = value;
234 *csr;
243 pctl.pctl_q_whole = port->pctl.csr;
296 saved_config[index].wsba[0] = port->wsba[0].csr;
297 saved_config[index].wsm[0] = port->wsm[0].csr;
207 volatile unsigned long *csr; local
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H A Dsys_marvel.c97 ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */
99 ctl = &io7->csrs->PO7_MSI_CTL[((irq - 0x80) >> 5) & 0x0f].csr;
175 volatile unsigned long *csr,
180 val = *csr;
184 *csr = val;
186 *csr;
197 val = io7->csrs->PO7_LSI_CTL[which].csr;
201 io7->csrs->PO7_LSI_CTL[which].csr = val;
203 io7->csrs->PO7_LSI_CTL[which].csr;
214 val = io7->csrs->PO7_MSI_CTL[which].csr;
173 io7_redirect_irq(struct io7 *io7, volatile unsigned long *csr, unsigned int where) argument
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H A Dsys_titan.c84 dim0 = &cchip->dim0.csr;
85 dim1 = &cchip->dim1.csr;
86 dim2 = &cchip->dim2.csr;
87 dim3 = &cchip->dim3.csr;
104 dimB = &cchip->dim0.csr;
105 if (bcpu == 1) dimB = &cchip->dim1.csr;
106 else if (bcpu == 2) dimB = &cchip->dim2.csr;
107 else if (bcpu == 3) dimB = &cchip->dim3.csr;
H A Dcore_marvel.c65 q = ev7csr->csr;
77 ev7csr->csr = q;
182 csrs->POx_ERR_SUM.csr = -1UL;
183 csrs->POx_TLB_ERR.csr = -1UL;
184 csrs->POx_SPL_COMPLT.csr = -1UL;
185 csrs->POx_TRANS_SUM.csr = -1UL;
193 p7csrs->PO7_ERROR_SUM.csr = -1UL;
194 p7csrs->PO7_UNCRR_SYM.csr = -1UL;
195 p7csrs->PO7_CRRCT_SYM.csr = -1UL;
267 io7_port->saved_wbase[i] = csrs->POx_WBASE[i].csr;
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H A Derr_marvel.c817 err_sum |= io7->csrs->PO7_ERROR_SUM.csr;
821 err_sum |= io7->ports[i].csrs->POx_ERR_SUM.csr;
842 io->io_asic_rev = io7->csrs->IO_ASIC_REV.csr;
843 io->io_sys_rev = io7->csrs->IO_SYS_REV.csr;
844 io->io7_uph = io7->csrs->IO7_UPH.csr;
845 io->hpi_ctl = io7->csrs->HPI_CTL.csr;
846 io->crd_ctl = io7->csrs->CRD_CTL.csr;
847 io->hei_ctl = io7->csrs->HEI_CTL.csr;
848 io->po7_error_sum = io7->csrs->PO7_ERROR_SUM.csr;
849 io->po7_uncrr_sym = io7->csrs->PO7_UNCRR_SYM.csr;
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H A Dsys_dp264.c68 dim0 = &cchip->dim0.csr;
69 dim1 = &cchip->dim1.csr;
70 dim2 = &cchip->dim2.csr;
71 dim3 = &cchip->dim3.csr;
88 if (bcpu == 0) dimB = &cchip->dim0.csr;
89 else if (bcpu == 1) dimB = &cchip->dim1.csr;
90 else if (bcpu == 2) dimB = &cchip->dim2.csr;
91 else dimB = &cchip->dim3.csr;
197 pld = TSUNAMI_cchip->dir0.csr;
/arch/m68k/sun3x/
H A Dtime.h9 volatile unsigned char csr; member in struct:mostek_dt
H A Dtime.c48 h->csr |= C_WRITE;
56 h->csr &= ~C_WRITE;
58 h->csr |= C_READ;
66 h->csr &= ~C_READ;
/arch/mips/cavium-octeon/executive/
H A Dcvmx-interrupt-rsl.c53 union cvmx_asxx_int_en csr; local
65 csr.u64 = cvmx_read_csr(CVMX_ASXX_INT_EN(block));
66 csr.s.txpsh = mask;
67 csr.s.txpop = mask;
68 csr.s.ovrflw = mask;
69 cvmx_write_csr(CVMX_ASXX_INT_EN(block), csr.u64);
/arch/mips/dec/
H A Dkn02-irq.c34 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + local
38 *csr = cached_kn02_csr;
43 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + local
47 *csr = cached_kn02_csr;
66 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + local
72 *csr = cached_kn02_csr;
H A Dkn01-berr.c53 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); local
58 *csr = cached_kn01_csr | KN01_CSR_MEMERR; /* Clear bus IRQ. */
154 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); local
158 if (!(*csr & KN01_CSR_MEMERR))
181 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); local
187 cached_kn01_csr = *csr;
193 *csr = cached_kn01_csr;
H A Decc-berr.c231 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); local
237 cached_kn02_csr = *csr | KN02_CSR_LEDS;
243 *csr = cached_kn02_csr;
/arch/sh/boards/mach-hp6xx/
H A Dpm.c42 u8 stbcr, csr; local
49 csr = sh_wdt_read_csr();
50 csr &= ~WTCSR_TME;
51 csr |= WTCSR_CKS_4096;
52 sh_wdt_write_csr(csr);
53 csr = sh_wdt_read_csr();
/arch/powerpc/boot/
H A Dugecon.c48 u32 csr, data, cr; local
51 csr = EXI_CSR_CLK_32MHZ | EXI_CSR_CS_0;
52 out_be32(csr_reg, csr);
/arch/mips/include/asm/sibyte/
H A Dsb1250_defs.h255 #define SBWRITECSR(csr, val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)
256 #define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
/arch/arm/boot/dts/
H A Dbcm59056.dtsi53 csr_reg: csr {
/arch/mips/kernel/
H A Dirq_txx9.c34 u32 csr; member in struct:txx9_irc_reg
186 u32 csr = __raw_readl(&txx9_ircptr->csr); local
188 if (likely(!(csr & TXx9_IRCSR_IF)))
189 return TXX9_IRQ_BASE + (csr & (TXx9_MAX_IR - 1));
/arch/arm64/boot/dts/
H A Dapm-storm.dtsi153 reg-names = "csr-reg";
175 reg-names = "csr-reg";
184 reg-names = "csr-reg";
185 csr-mask = <0x3>;
194 reg-names = "csr-reg";
195 csr-mask = <0x3>;
204 reg-names = "csr-reg";
207 csr-offset = <0x4>;
208 csr-mask = <0x00>;
218 reg-names = "csr
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/arch/powerpc/platforms/embedded6xx/
H A Dusbgecko_udbg.c55 u32 csr, data, cr; local
58 csr = EXI_CSR_CLK_32MHZ | EXI_CSR_CS_0;
59 out_be32(csr_reg, csr);
/arch/c6x/kernel/
H A Dsetup.c90 unsigned cpu_id, rev_id, csr; local
113 csr = get_creg(CSR);
114 cpu_id = csr >> 24;
115 rev_id = (csr >> 16) & 0xff;
/arch/arm/plat-omap/
H A Ddma.c1097 u32 csr; local
1100 csr = dma_chan[ch].saved_csr;
1103 csr = p->dma_read(CSR, ch);
1104 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1105 dma_chan[ch + 6].saved_csr = csr >> 7;
1106 csr &= 0x7f;
1108 if ((csr & 0x3f) == 0)
1112 ch, csr);
1115 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1117 if (unlikely(csr
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