Searched refs:enable_mask (Results 1 - 9 of 9) sorted by relevance
| /arch/arm/mach-lpc32xx/ |
| H A D | clock.h | 35 u32 enable_mask; member in struct:clk
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| H A D | clock.c | 550 tmp &= ~clk->enable_mask;
552 tmp |= clk->enable_mask;
564 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN,
571 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
578 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN,
585 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
592 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN,
599 .enable_mask = LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
606 .enable_mask = LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT,
613 .enable_mask
[all...] |
| /arch/arm/mach-ep93xx/ |
| H A D | clock.c | 36 u32 enable_mask; member in struct:clk
57 .enable_mask = EP93XX_SYSCON_DEVCFG_U1EN,
64 .enable_mask = EP93XX_SYSCON_DEVCFG_U2EN,
71 .enable_mask = EP93XX_SYSCON_DEVCFG_U3EN,
92 .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN,
98 .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
113 .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
120 .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
128 .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA,
136 .enable_mask
[all...] |
| /arch/arm/mach-omap2/ |
| H A D | clkt_dpll.c | 215 v &= dd->enable_mask;
216 v >>= __ffs(dd->enable_mask);
251 v &= dd->enable_mask;
252 v >>= __ffs(dd->enable_mask);
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| H A D | dpll3xxx.c | 51 v &= ~dd->enable_mask;
52 v |= clken_bits << __ffs(dd->enable_mask);
692 WARN_ON(!dd->enable_mask);
694 v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask;
695 v >>= __ffs(dd->enable_mask);
732 WARN_ON(!dd->enable_mask);
734 v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask;
735 v >>= __ffs(dd->enable_mask);
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| H A D | display.c | 109 u32 enable_mask, enable_shift; local
114 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
119 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
129 reg &= ~enable_mask;
132 reg |= (lanes << enable_shift) & enable_mask;
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| H A D | cclock3xxx_data.c | 97 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
237 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
323 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
344 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
816 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
965 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
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| /arch/x86/kernel/cpu/ |
| H A D | perf_event_amd_ibs.c | 49 u64 enable_mask; member in struct:perf_ibs
340 wrmsrl(hwc->config_base, hwc->config | config | perf_ibs->enable_mask);
355 config &= ~perf_ibs->enable_mask;
482 .enable_mask = IBS_FETCH_ENABLE,
506 .enable_mask = IBS_OP_ENABLE,
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| H A D | perf_event.h | 592 u64 enable_mask)
598 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
591 __x86_pmu_enable_event(struct hw_perf_event *hwc, u64 enable_mask) argument
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