Searched refs:instruction (Results 1 - 25 of 100) sorted by relevance

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/arch/ia64/scripts/
H A Dcheck-serialize.S2 .serialize.instruction
/arch/m68k/fpsp040/
H A Dsmovecr.S5 | offset given in the instruction field.
7 | Input: An offset in the instruction word.
H A Dbugfix.S65 | /* If the xu instruction is exceptional, we punt.
114 | /* If the xu instruction is exceptional, we punt.
247 | dest and the dest of the xu. We must clear the instruction in
248 | the cu and restore the state, allowing the instruction in the
249 | xu to complete. Remember, the instruction in the nu
251 | If the result of the xu instruction is not exceptional, we can
252 | restore the instruction from the cu to the frame and continue
275 | Check if the instruction which just completed was exceptional.
280 | It is necessary to isolate the result of the instruction in the
369 | dest and the dest of the xu. We must clear the instruction i
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/arch/sh/kernel/
H A Dtraps_32.c80 * handle an instruction that does an unaligned memory access by emulating the
82 * - note that PC _may not_ point to the faulting instruction
83 * (if that instruction is in a branch delay slot)
86 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs, argument
94 index = (instruction>>8)&15; /* 0x0F00 */
97 index = (instruction>>4)&15; /* 0x00F0 */
100 count = 1<<(instruction&3);
110 switch (instruction>>12) {
112 if (instruction & 8) {
144 dstu += (instruction
270 insn_size_t instruction; local
303 handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, struct mem_access *ma, int expected, unsigned long address) argument
479 insn_size_t instruction; local
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H A Dio_trapped.c274 insn_size_t instruction; local
286 if (copy_from_user(&instruction, (void *)(regs->pc),
287 sizeof(instruction))) {
292 tmp = handle_unaligned_access(instruction, regs,
/arch/mips/dec/prom/
H A Dlocore.S26 addiu k0, 4 # skip the causing instruction
/arch/arm/mm/
H A Dabort-ev4.S12 * Purpose : obtain information about current aborted instruction.
21 ldr r3, [r4] @ read aborted ARM instruction
H A Dabort-ev4t.S13 * Purpose : obtain information about current aborted instruction.
23 ldreq r3, [r4] @ read aborted ARM instruction
H A Dabort-ev5t.S13 * Purpose : obtain information about current aborted instruction.
23 ldreq r3, [r4] @ read aborted ARM instruction
H A Dabort-ev5tj.S13 * Purpose : obtain information about current aborted instruction.
26 ldreq r3, [r4] @ read aborted ARM instruction
H A Dabort-macro.S3 * differently than every other instruction, so it is set to 0 (write)
15 ldrh \tmp, [\pc] @ Read aborted Thumb instruction
26 * We check for the following instruction encoding for LDRD.
H A Dabort-ev6.S13 * Purpose : obtain information about current aborted instruction.
23 * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR.
34 ldr r3, [r4] @ read aborted ARM instruction
H A Dabort-lv4t.S12 * Purpose : obtain information about current aborted instruction.
28 ldr r8, [r4] @ read arm instruction
71 and r9, r8, #15 << 16 @ Extract 'n' from instruction
89 and r9, r8, #15 << 16 @ Extract 'n' from instruction
103 and r9, r8, #15 << 16 @ Extract 'n' from instruction
115 and r7, r8, #15 @ Extract 'm' from instruction
157 ldrh r8, [r4] @ read instruction
/arch/arm/nwfpe/
H A Dentry.S29 ldrt r0, [r4] @ r0 = instruction
44 the user code. If the emulator is unable to emulate the instruction,
60 2) It calls EmulateAll to emulate a floating point instruction.
63 3) If an instruction has been emulated successfully, it looks ahead at
64 the next instruction. If it is a floating point instruction, it
65 executes the instruction, without returning to user space. In this
67 until it encounters a non floating point instruction, at which time it
90 bne next @ get the next instruction;
93 bl EmulateAll @ emulate the instruction
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/arch/s390/include/asm/
H A Ddis.h45 int insn_to_mnemonic(unsigned char *instruction, char *buf, unsigned int len);
/arch/powerpc/xmon/
H A Dppc.h122 /* Opcode is an e500 SPE floating point instruction. */
149 /* A macro to extract the major opcode from an instruction. */
160 /* How far the operand is left shifted in the instruction. */
164 operand value into an instruction, check this field.
168 (i is the instruction which we are filling in, o is a pointer to
173 instruction and the operand value. It will return the new value
174 of the instruction. If the ERRMSG argument is not NULL, then if
180 (unsigned long instruction, long op, int dialect, const char **errmsg);
183 extract this operand type from an instruction, check this field.
190 (i is the instruction,
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/arch/x86/kernel/kprobes/
H A Dcommon.h69 /* Ensure if the instruction can be boostable */
70 extern int can_boost(kprobe_opcode_t *instruction);
71 /* Recover instruction if given address is probed */
75 * Copy an instruction and adjust the displacement if the instruction
80 /* Generate a relative-jump/call instruction */
/arch/arm/vfp/
H A Dentry.S20 @ r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
24 @ lr = unrecognised instruction return address
/arch/openrisc/
H A DKconfig81 bool "Have instruction l.ff1"
84 Select this if your implementation has the Class II instruction l.ff1
87 bool "Have instruction l.fl1"
90 Select this if your implementation has the Class II instruction l.fl1
93 bool "Have instruction l.mul for hardware multiply"
96 Select this if your implementation has a hardware multiply instruction
99 bool "Have instruction l.div for hardware divide"
102 Select this if your implementation has a hardware divide instruction
/arch/frv/kernel/
H A Dcmode.S88 # (4) Preload a series of following instructions to the instruction
111 # (5) Flush the content of all caches by the DCEF instruction.
123 # (8) Execute memory barrier instruction (MEMBAR).
132 # (10) Execute memory barrier instruction (MEMBAR).
144 # (13) Execute the instruction just after the memory barrier
145 # instruction that executes the self-loop 256 times. (Meanwhile,
/arch/arm/kernel/
H A Dkprobes-test.h94 * After this, the instruction to be tested is defined with TEST_INSTRUCTION.
150 #define TEST_INSTRUCTION(instruction) \
152 "1: "instruction" \n\t" \
155 #define TEST_BRANCH_F(instruction) \
156 TEST_INSTRUCTION(instruction) \
160 #define TEST_BRANCH_B(instruction) \
165 TEST_INSTRUCTION(instruction)
167 #define TEST_BRANCH_FX(instruction, codex) \
168 TEST_INSTRUCTION(instruction) \
174 #define TEST_BRANCH_BX(instruction, code
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H A Dentry-armv.S14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
234 @ Correct the PC such that it is pointing at the instruction
235 @ which caused the fault. If the faulting instruction was ARM
236 @ the PC will be pointing at the next instruction, and have to
238 @ pointing at the second half of the Thumb instruction. We
249 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
258 @ the instruction, or the more conventional lr if we are to treat
259 @ this as a real undefined instruction
261 @ r0 - instruction
267 ldrh r0, [r4, #-2] @ Thumb instruction a
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/arch/m68k/ifpsp060/src/
H A Disp.S337 # _imem_read_{word,long}() - read instruction word/longword #
366 # This handler fetches the first instruction longword from #
426 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
427 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
549 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
550 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
599 # The instruction that was just emulated was also being traced. The trace
600 # trap for this instruction will be lost unless we jump to the trace handler.
648 # the chk2 instruction should take a chk trap. so, here we must create a
649 # chk stack frame from an unimplemented integer instruction exceptio
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/arch/s390/kernel/
H A Dmcount.S51 # The j instruction gets runtime patched to a nop instruction.
/arch/powerpc/lib/
H A Dcode-patching.c38 unsigned int instruction; local
45 /* Check we can represent the target in the instruction format */
50 instruction = 0x48000000 | (flags & 0x3) | (offset & 0x03FFFFFC);
52 return instruction;
58 unsigned int instruction; local
65 /* Check we can represent the target in the instruction format */
70 instruction = 0x40000000 | (flags & 0x3FF0003) | (offset & 0xFFFC);
72 return instruction;
170 * the second instruction. Thus we need to patch the second
171 * instruction o
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