Searched refs:mpidr (Results 1 - 22 of 22) sorted by relevance

/arch/arm/common/
H A Dmcpm_platsmp.c25 unsigned int mpidr; local
27 mpidr = cpu_logical_map(cpu);
28 *pcpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
29 *pcluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
80 unsigned int mpidr, pcpu, pcluster; local
81 mpidr = read_cpuid_mpidr();
82 pcpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
83 pcluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
H A Dmcpm_entry.c156 unsigned int mpidr = read_cpuid_mpidr(); local
157 unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
158 unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
320 unsigned int i, j, mpidr, this_cluster; local
335 mpidr = read_cpuid_mpidr();
336 this_cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
H A DbL_switcher.c126 unsigned int mpidr = read_mpidr(); local
127 unsigned int clusterid = MPIDR_AFFINITY_LEVEL(mpidr, 1);
151 unsigned int mpidr, this_cpu, that_cpu; local
246 mpidr = read_mpidr();
247 pr_debug("after switch: CPU %d MPIDR %#x\n", this_cpu, mpidr);
248 BUG_ON(mpidr != ib_mpidr);
530 int bL_switcher_get_logical_index(u32 mpidr) argument
537 mpidr &= MPIDR_HWID_BITMASK;
542 if ((mpidr == cpu_logical_map(cpu)) ||
543 (mpidr
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/arch/arm/include/asm/
H A DbL_switcher.h58 int bL_switcher_get_logical_index(u32 mpidr);
74 static inline int bL_switcher_get_logical_index(u32 mpidr) { return -EUNATCH; } argument
H A Dsmp_plat.h75 * - mpidr: MPIDR[23:0] to be used for the look-up
79 static inline int get_logical_index(u32 mpidr) argument
83 if (cpu_logical_map(cpu) == mpidr)
H A Dcputype.h59 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
60 ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
/arch/arm/mach-exynos/
H A Dhotplug.c42 u32 mpidr = cpu_logical_map(cpu); local
43 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
H A Dmcpm-exynos.c133 unsigned int mpidr, cpu, cluster; local
137 mpidr = read_cpuid_mpidr();
138 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
139 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
192 cci_disable_port_by_cpu(mpidr);
236 unsigned int mpidr, cpu, cluster; local
238 mpidr = read_cpuid_mpidr();
239 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
240 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
250 unsigned int mpidr, cpun local
278 unsigned int mpidr, cpu, cluster; local
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H A Dplatsmp.c160 u32 mpidr = cpu_logical_map(cpu); local
161 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
300 u32 mpidr; local
304 mpidr = cpu_logical_map(i);
305 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
H A Dregs-pmu.h323 static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr) argument
325 return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
326 + MPIDR_AFFINITY_LEVEL(mpidr, 0));
/arch/arm/mach-vexpress/
H A Dtc2_pm.c109 unsigned int mpidr, cpu, cluster; local
112 mpidr = read_cpuid_mpidr();
113 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
114 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
169 cci_disable_port_by_cpu(mpidr);
251 unsigned int mpidr, cpu, cluster; local
253 mpidr = read_cpuid_mpidr();
254 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
255 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
262 unsigned int mpidr, cp local
300 unsigned int mpidr, cpu, cluster; local
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H A Ddcscb.c99 unsigned int mpidr, cpu, cluster, rst_hold, cpumask, all_mask; local
102 mpidr = read_cpuid_mpidr();
103 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
104 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
158 cci_disable_port_by_cpu(mpidr);
185 unsigned int mpidr, cpu, cluster; local
187 mpidr = read_cpuid_mpidr();
188 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
189 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
/arch/arm/kernel/
H A Dtopology.c231 unsigned int mpidr; local
237 mpidr = read_cpuid_mpidr();
240 if ((mpidr & MPIDR_SMP_BITMASK) == MPIDR_SMP_VALUE) {
246 if (mpidr & MPIDR_MT_BITMASK) {
248 cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
249 cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
250 cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
254 cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
255 cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
272 printk(KERN_INFO "CPU%u: thread %d, cpu %d, socket %d, mpidr
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H A Dsleep.S17 * @mpidr: register containing MPIDR value
24 *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 mpidr, u32 mask) {
26 * u32 mpidr_masked = mpidr & mask;
32 * Input registers: rs0, rs1, rs2, mpidr, mask
35 (eg: a macro instance with mpidr = r1 and dst = r1 is invalid)
37 .macro compute_mpidr_hash dst, rs0, rs1, rs2, mpidr, mask
38 and \mpidr, \mpidr, \mask @ mask out MPIDR bits
39 and \dst, \mpidr, #0xff @ mask=aff0
42 and \mask, \mpidr, #
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H A Ddevtree.c80 u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0; local
135 if (hwid == mpidr) {
H A Dsetup.c498 u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0; local
499 u32 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
512 pr_info("Booting Linux on physical CPU 0x%x\n", mpidr);
/arch/arm/mach-hisi/
H A Dplatmcpm.c143 unsigned int mpidr, cpu, cluster; local
146 mpidr = read_cpuid_mpidr();
147 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
148 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
232 unsigned int mpidr, cpu, cluster; local
234 mpidr = read_cpuid_mpidr();
235 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
236 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
285 unsigned int mpidr, cpu, cluster; local
287 mpidr
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/arch/arm64/kernel/
H A Dtopology.c242 u64 mpidr; local
247 mpidr = read_cpuid_mpidr();
250 if (mpidr & MPIDR_UP_BITMASK)
254 if (mpidr & MPIDR_MT_BITMASK) {
256 cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
257 cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
258 cpuid_topo->cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
262 cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
263 cpuid_topo->cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
266 pr_debug("CPU%u: cluster %d core %d thread %d mpidr
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H A Dsleep.S16 * @mpidr: register containing MPIDR_EL1 value
23 *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 rs3, u64 mpidr, u64 mask) {
25 * u64 mpidr_masked = mpidr & mask;
32 * Input registers: rs0, rs1, rs2, rs3, mpidr, mask
35 (eg: a macro instance with mpidr = x1 and dst = x1 is invalid)
37 .macro compute_mpidr_hash dst, rs0, rs1, rs2, rs3, mpidr, mask
38 and \mpidr, \mpidr, \mask // mask out MPIDR bits
39 and \dst, \mpidr, #0xff // mask=aff0
41 and \mask, \mpidr, #
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/arch/arm/kvm/
H A Dpsci.c72 unsigned long mpidr; local
81 mpidr = kvm_vcpu_get_mpidr(tmp);
82 if ((mpidr & MPIDR_HWID_BITMASK) == (cpu_id & MPIDR_HWID_BITMASK)) {
134 unsigned long mpidr; local
157 mpidr = kvm_vcpu_get_mpidr(tmp);
158 if (((mpidr & target_affinity_mask) == target_affinity) &&
/arch/arm64/include/asm/
H A Dcputype.h32 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
33 ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
/arch/arm/mach-shmobile/
H A Dheadsmp.S60 adr r5, 1f @ array of per-cpu mpidr values

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