/arch/parisc/include/asm/ |
H A D | asmregs.h | 24 rp: .reg %r2 25 arg3: .reg %r23 26 arg2: .reg %r24 27 arg1: .reg %r25 28 arg0: .reg %r26 29 dp: .reg %r27 30 ret0: .reg %r28 31 ret1: .reg %r29 32 sl: .reg %r29 33 sp: .reg [all...] |
/arch/mips/include/asm/ |
H A D | asm-eva.h | 16 #define __BUILD_EVA_INSN(insn, reg, addr) \ 20 " "insn" "reg", "addr "\n" \ 24 #define user_ll(reg, addr) __BUILD_EVA_INSN("lle", reg, addr) 25 #define user_sc(reg, addr) __BUILD_EVA_INSN("sce", reg, addr) 26 #define user_lw(reg, addr) __BUILD_EVA_INSN("lwe", reg, addr) 27 #define user_lwl(reg, addr) __BUILD_EVA_INSN("lwle", reg, add [all...] |
H A D | reg.h | 1 #include <uapi/asm/reg.h>
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/arch/x86/boot/ |
H A D | regs.c | 22 void initregs(struct biosregs *reg) argument 24 memset(reg, 0, sizeof *reg); 25 reg->eflags |= X86_EFLAGS_CF; 26 reg->ds = ds(); 27 reg->es = ds(); 28 reg->fs = fs(); 29 reg->gs = gs();
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/arch/arm/boot/dts/ |
H A D | kirkwood-ts419-6281.dts | 19 ðphy0 { reg = <8>; }; 20 ðphy1 { reg = <0>; };
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H A D | tps65910.dtsi | 22 reg = <0>; 27 reg = <1>; 32 reg = <2>; 37 reg = <3>; 42 reg = <4>; 47 reg = <5>; 52 reg = <6>; 57 reg = <7>; 62 reg = <8>; 67 reg [all...] |
/arch/metag/include/asm/ |
H A D | core_reg.h | 6 extern void core_reg_write(int unit, int reg, int thread, unsigned int val); 7 extern unsigned int core_reg_read(int unit, int reg, int thread); 14 #define __core_reg_get(reg) ({ \ 16 asm volatile("MOV %0," #reg \ 21 #define __core_reg_set(reg, value) do { \ 23 asm volatile("MOV " #reg ",%0" \ 28 #define __core_reg_swap(reg, value) do { \ 30 asm volatile("SWAP " #reg ",%0" \
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/arch/mips/include/asm/mach-ralink/ |
H A D | ralink_regs.h | 19 static inline void rt_sysc_w32(u32 val, unsigned reg) argument 21 __raw_writel(val, rt_sysc_membase + reg); 24 static inline u32 rt_sysc_r32(unsigned reg) argument 26 return __raw_readl(rt_sysc_membase + reg); 29 static inline void rt_memc_w32(u32 val, unsigned reg) argument 31 __raw_writel(val, rt_memc_membase + reg); 34 static inline u32 rt_memc_r32(unsigned reg) argument 36 return __raw_readl(rt_memc_membase + reg);
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/arch/x86/include/asm/ |
H A D | processor-cyrix.h | 20 static inline u8 getCx86(u8 reg) argument 22 outb(reg, 0x22); 26 static inline void setCx86(u8 reg, u8 data) argument 28 outb(reg, 0x22); 32 #define getCx86_old(reg) ({ outb((reg), 0x22); inb(0x23); }) 34 #define setCx86_old(reg, data) do { \ 35 outb((reg), 0x22); \
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H A D | intel_mid_vrtc.h | 4 extern unsigned char vrtc_cmos_read(unsigned char reg); 5 extern void vrtc_cmos_write(unsigned char val, unsigned char reg);
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/arch/m32r/kernel/ |
H A D | entry.S | 83 #define R4(reg) @reg 84 #define R5(reg) @(0x04,reg) 85 #define R6(reg) @(0x08,reg) 86 #define PTREGS(reg) @(0x0C,reg) 87 #define R0(reg) @(0x10,reg) [all...] |
/arch/ia64/include/asm/native/ |
H A D | pvchk_inst.h | 126 /* check whether reg is a regular register */ 127 .macro is_rreg_in reg 128 .ifc "\reg", "r0" 133 mov \reg = r0 variable 136 #define IS_RREG_IN(reg) is_rreg_in reg ; 138 #define IS_RREG_OUT(reg) \ 140 mov reg = r0 \ 143 #define IS_RREG_CLOB(reg) IS_RREG_OUT(reg) [all...] |
/arch/powerpc/boot/dts/ |
H A D | p1010rdb-pa.dtsi | 39 reg = <0x0 0x00100000>; 46 reg = <0x00100000 0x00100000>; 52 reg = <0x00200000 0x00400000>; 58 reg = <0x00600000 0x00400000>; 64 reg = <0x00a00000 0x00f00000>; 70 reg = <0x01900000 0x00700000>;
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/arch/powerpc/boot/dts/fsl/ |
H A D | pq3-etsec1-timer-0.dtsi | 37 reg = <0x24e00 0xb0>;
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H A D | pq3-mpic-timer-B.dtsi | 37 reg = <0x42100 0x100 0x42300 4>;
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H A D | qoriq-sata2-0.dtsi | 37 reg = <0x220000 0x1000>;
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H A D | qoriq-sata2-1.dtsi | 37 reg = <0x221000 0x1000>;
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/arch/sh/include/mach-common/mach/ |
H A D | magicpanelr2.h | 22 #define SETBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) | mask, reg) 23 #define SETBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) | mask, reg) 24 #define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) | mask, reg) 25 #define CLRBITS_OUTB(mask, reg) __raw_write [all...] |
/arch/mips/boot/dts/ |
H A D | xlp_evp.dts | 22 reg = <0 0x30100 0xa00>; 23 reg-shift = <2>; 24 reg-io-width = <4>; 32 reg = <0 0x31100 0xa00>; 33 reg-shift = <2>; 34 reg-io-width = <4>; 43 reg = <0 0x32100 0xa00>; 44 reg-shift = <2>; 45 reg-io-width = <4>; 54 reg [all...] |
H A D | xlp_fvp.dts | 22 reg = <0 0x30100 0xa00>; 23 reg-shift = <2>; 24 reg-io-width = <4>; 32 reg = <0 0x31100 0xa00>; 33 reg-shift = <2>; 34 reg-io-width = <4>; 43 reg = <0 0x37100 0x20>; 44 reg-shift = <2>; 45 reg-io-width = <4>; 54 reg [all...] |
H A D | xlp_svp.dts | 22 reg = <0 0x30100 0xa00>; 23 reg-shift = <2>; 24 reg-io-width = <4>; 32 reg = <0 0x31100 0xa00>; 33 reg-shift = <2>; 34 reg-io-width = <4>; 43 reg = <0 0x32100 0xa00>; 44 reg-shift = <2>; 45 reg-io-width = <4>; 54 reg [all...] |
/arch/cris/include/arch-v32/arch/hwregs/iop/ |
H A D | iop_version_defs.h | 18 #define REG_RD( scope, inst, reg ) \ 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all...] |
/arch/cris/include/arch-v32/arch/hwregs/ |
H A D | irq_nmi_defs.h | 18 #define REG_RD( scope, inst, reg ) \ 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all...] |
H A D | strcop_defs.h | 18 #define REG_RD( scope, inst, reg ) \ 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all...] |
/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/ |
H A D | iop_version_defs.h | 15 #define REG_RD( scope, inst, reg ) \ 16 REG_READ( reg_##scope##_##reg, \ 17 (inst) + REG_RD_ADDR_##scope##_##reg ) 21 #define REG_WR( scope, inst, reg, val ) \ 22 REG_WRITE( reg_##scope##_##reg, \ 23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27 #define REG_RD_VECT( scope, inst, reg, index ) \ 28 REG_READ( reg_##scope##_##reg, \ 29 (inst) + REG_RD_ADDR_##scope##_##reg + \ 30 (index) * STRIDE_##scope##_##reg ) [all...] |