Searched refs:reg1 (Results 1 - 25 of 37) sorted by relevance

12

/arch/m32r/include/asm/
H A Ddcache_clear.h13 #define DCACHE_CLEAR(reg0, reg1, addr) \
14 "seth "reg1", #high(dcache_dummy); \n\t" \
15 "or3 "reg1", "reg1", #low(dcache_dummy); \n\t" \
16 "lock "reg0", @"reg1"; \n\t" \
21 "unlock "reg0", @"reg1"; \n\t"
26 #define DCACHE_CLEAR(reg0, reg1, addr)
/arch/arm/lib/
H A Dcsumpartialcopy.S28 .macro load1b, reg1
29 ldrb \reg1, [r0], #1
32 .macro load2b, reg1, reg2
33 ldrb \reg1, [r0], #1
37 .macro load1l, reg1
38 ldr \reg1, [r0], #4
41 .macro load2l, reg1, reg2
42 ldr \reg1, [r0], #4
46 .macro load4l, reg1, reg2, reg3, reg4
47 ldmia r0!, {\reg1, \reg
[all...]
H A Dcsumpartialcopyuser.S28 .macro load1b, reg1
29 ldrusr \reg1, r0, 1
32 .macro load2b, reg1, reg2
33 ldrusr \reg1, r0, 1
37 .macro load1l, reg1
38 ldrusr \reg1, r0, 4
41 .macro load2l, reg1, reg2
42 ldrusr \reg1, r0, 4
46 .macro load4l, reg1, reg2, reg3, reg4
47 ldrusr \reg1, r
[all...]
H A Dmemcpy.S23 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
24 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
27 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
28 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
39 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
40 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
47 .macro enter reg1 reg2
48 stmdb sp!, {r0, \reg1, \reg2}
51 .macro exit reg1 reg2
52 ldmfd sp!, {r0, \reg1, \reg
[all...]
H A Dcopy_from_user.S47 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
48 ldr1w \ptr, \reg1, \abort
54 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
55 ldr4w \ptr, \reg1, \reg2, \reg3, \reg4, \abort
67 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
68 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
75 .macro enter reg1 reg2
77 stmdb sp!, {r0, r2, r3, \reg1, \reg2}
80 .macro exit reg1 reg2
82 ldmfd sp!, {r0, \reg1, \reg
[all...]
H A Dcopy_to_user.S47 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
48 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
51 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
52 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
63 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
64 str1w \ptr, \reg1, \abort
78 .macro enter reg1 reg2
80 stmdb sp!, {r0, r2, r3, \reg1, \reg2}
83 .macro exit reg1 reg2
85 ldmfd sp!, {r0, \reg1, \reg
[all...]
/arch/arm/kernel/
H A Dhyp-stub.S40 .macro store_primary_cpu_mode reg1, reg2, reg3
41 mrs \reg1, cpsr
42 and \reg1, \reg1, #MODE_MASK
45 str \reg1, [\reg2, \reg3]
54 .macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3
57 ldr \reg1, [\reg2, \reg3]
58 cmp \mode, \reg1 @ matches primary CPU boot mode?
59 orrne \reg1, \reg1, #BOOT_CPU_MODE_MISMATC
[all...]
H A Dkprobes-test.h234 #define TEST_RR(code1, reg1, val1, code2, reg2, val2, code3) \
235 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
236 TEST_ARG_REG(reg1, val1) \
239 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \
242 #define TEST_RRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\
243 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
244 TEST_ARG_REG(reg1, val1) \
248 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
251 #define TEST_RRRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4, reg4, val4) \
252 TESTCASE_START(code1 #reg1 code
[all...]
/arch/s390/include/asm/
H A Dsigp.h40 register unsigned long reg1 asm ("1") = parm;
47 : "=d" (cc), "+d" (reg1) : "d" (addr), "a" (order) : "cc");
49 *status = reg1;
H A Detr.h192 register unsigned long reg1 asm("1") = (unsigned long) ptff_block;
200 : "d" (reg0), "d" (reg1), "m" (ptff_block) : "cc");
H A Dpage.h42 register unsigned long reg1 asm ("1") = 0;
47 : "+d" (reg2), "+d" (reg3) : "d" (reg1)
/arch/x86/kernel/cpu/
H A Dperf_event_intel_uncore_nhmex.c346 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
361 reg1->reg = NHMEX_B0_MSR_MATCH;
363 reg1->reg = NHMEX_B1_MSR_MATCH;
364 reg1->idx = 0;
365 reg1->config = event->attr.config1;
373 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
376 if (reg1->idx != EXTRA_REG_NONE) {
377 wrmsrl(reg1->reg, reg1->config);
378 wrmsrl(reg1
437 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
458 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
625 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
664 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
733 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
761 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
831 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
940 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
974 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
1058 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
1082 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
1107 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
[all...]
H A Dperf_event_intel_uncore_snbep.c351 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
353 if (reg1->idx != EXTRA_REG_NONE)
354 wrmsrl(reg1->reg, uncore_shared_reg_config(box, 0));
638 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
646 if (reg1->alloc & (0x1 << i))
649 reg1->alloc = 0;
656 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
662 if (reg1->idx == EXTRA_REG_NONE)
667 if (!(reg1->idx & (0x1 << i)))
669 if (!uncore_box_is_fake(box) && (reg1
723 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
768 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
787 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
828 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
841 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
895 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
912 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
1377 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
1399 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
1730 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
1863 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
1886 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
1981 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
[all...]
H A Dperf_event_intel_uncore.c86 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
96 if (reg1->idx == EXTRA_REG_NONE ||
97 (!uncore_box_is_fake(box) && reg1->alloc))
100 er = &box->shared_regs[reg1->idx];
103 (er->config1 == reg1->config && er->config2 == reg2->config)) {
105 er->config1 = reg1->config;
113 reg1->alloc = 1;
123 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
133 if (uncore_box_is_fake(box) || !reg1->alloc)
136 er = &box->shared_regs[reg1
[all...]
/arch/unicore32/lib/
H A Dcopy_from_user.S40 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
41 100: ldm.w (\reg1, \reg2, \reg3, \reg4), [\ptr]+
48 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
49 100: ldm.w (\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8), [\ptr]+
64 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
65 stm.w (\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8), [\ptr]+
H A Dcopy_to_user.S40 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
41 ldm.w (\reg1, \reg2, \reg3, \reg4), [\ptr]+
44 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
45 ldm.w (\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8), [\ptr]+
57 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
58 100: stm.w (\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8), [\ptr]+
/arch/s390/kvm/
H A Dtrace.h284 TP_PROTO(VCPU_PROTO_COMMON, int g, int reg1, int reg3, u64 addr),
285 TP_ARGS(VCPU_ARGS_COMMON, g, reg1, reg3, addr),
290 __field(int, reg1)
298 __entry->reg1 = reg1;
305 __entry->reg1, __entry->reg3, __entry->addr)
309 TP_PROTO(VCPU_PROTO_COMMON, int g, int reg1, int reg3, u64 addr),
310 TP_ARGS(VCPU_ARGS_COMMON, g, reg1, reg3, addr),
315 __field(int, reg1)
323 __entry->reg1
[all...]
H A Dpriv.c597 int reg1, reg2; local
599 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2);
602 vcpu->run->s.regs.gprs[reg1] &= 0xffffffff00000000UL;
603 vcpu->run->s.regs.gprs[reg1] |= vcpu->arch.sie_block->gpsw.mask >> 32;
624 int reg1, reg2; local
629 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2);
637 if (vcpu->run->s.regs.gprs[reg1] & PFMF_RESERVED)
641 if (vcpu->run->s.regs.gprs[reg1] & PFMF_NQ && !test_facility(14))
645 if (vcpu->run->s.regs.gprs[reg1] & (PFMF_MR | PFMF_MC))
649 if (vcpu->run->s.regs.gprs[reg1]
763 int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; local
800 int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; local
836 int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; local
872 int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; local
[all...]
H A Dintercept.c293 int reg1, reg2, rc; local
295 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2);
306 dstaddr = kvm_s390_real_to_abs(vcpu, vcpu->run->s.regs.gprs[reg1]);
/arch/m32r/kernel/
H A Dalign.c277 int reg1, reg2; local
279 reg1 = get_reg(regs, dest);
284 : "+r" (reg1) : "r" (reg2)
287 set_reg(regs, dest, reg1);
294 int reg1, reg2; local
296 reg1 = get_reg(regs, REG1(insn));
303 : "+r" (reg1), "+r" (reg2)
306 regs->acc0h = reg1;
314 int reg1, reg2; local
316 reg1
[all...]
H A Dptrace.c225 unsigned long reg1, reg2; local
231 reg1 = get_stack_long(child, reg_offset[regno1]);
232 return reg1 == reg2;
234 reg1 = get_stack_long(child, reg_offset[regno1]);
235 return reg1 != reg2;
/arch/ia64/include/asm/native/
H A Dpvchk_inst.h227 #define THASH(pred, reg0, reg1, clob) \
230 IS_RREG_IN(reg1) \
H A Dinst.h127 #define THASH(pred, reg0, reg1, clob) \
128 (pred) thash reg0 = reg1 \
/arch/x86/kernel/apic/
H A Dapic.c1124 unsigned int reg0, reg1; local
1132 reg1 = apic_read(APIC_LVR);
1133 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
1140 if (reg1 != reg0)
1146 reg1 = GET_APIC_VERSION(reg0);
1147 if (reg1 == 0x00 || reg1 == 0xff)
1149 reg1 = lapic_get_maxlvt();
1150 if (reg1 < 0x02 || reg1
[all...]
/arch/xtensa/lib/
H A Dmemset.S33 #define EX(insn,reg1,reg2,offset,handler) \
34 9: insn reg1, reg2, offset; \

Completed in 1259 milliseconds

12