/arch/arm/mach-at91/ |
H A D | pm_slowclock.S | 46 tmp1 .req r4 label 57 ldr tmp1, [pmc, #AT91_PMC_SR] 58 tst tmp1, #AT91_PMC_MCKRDY 71 ldr tmp1, [pmc, #AT91_PMC_SR] 72 tst tmp1, #AT91_PMC_MOSCS 85 ldr tmp1, [pmc, #AT91_PMC_SR] 86 tst tmp1, #AT91_PMC_LOCKA 99 ldr tmp1, [pmc, #AT91_PMC_SR] 100 tst tmp1, #AT91_PMC_LOCKB 125 mov tmp1, # [all...] |
/arch/sparc/include/asm/ |
H A D | head_64.h | 30 #define BRANCH_IF_SUN4V(tmp1,label) \ 31 sethi %hi(is_sun4v), %tmp1; \ 32 lduw [%tmp1 + %lo(is_sun4v)], %tmp1; \ 33 brnz,pn %tmp1, label; \ 36 #define BRANCH_IF_CHEETAH_BASE(tmp1,tmp2,label) \ 37 rdpr %ver, %tmp1; \ 39 srlx %tmp1, 32, %tmp1; \ 41 cmp %tmp1, [all...] |
H A D | spinlock_64.h | 73 unsigned long tmp1, tmp2; local 88 : "=&r" (tmp1), "=&r" (tmp2) 97 unsigned long tmp1, tmp2; local 113 : "=&r" (tmp1), "=&r" (tmp2) 120 int tmp1, tmp2; local 132 : "=&r" (tmp1), "=&r" (tmp2) 136 return tmp1; 141 unsigned long tmp1, tmp2; local 150 : "=&r" (tmp1), "=&r" (tmp2) 157 unsigned long mask, tmp1, tmp local 191 unsigned long mask, tmp1, tmp2, result; local [all...] |
H A D | pgtsrmmu.h | 130 #define WINDOW_FLUSH(tmp1, tmp2) \ 131 mov 0, tmp1; \ 134 add tmp1, 1, tmp1; \ 137 99: subcc tmp1, 1, tmp1; \
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/arch/arm/mach-tegra/ |
H A D | sleep.h | 88 .macro check_cpu_part_num part_num, tmp1, tmp2 variable 89 mrc p15, 0, \tmp1, c0, c0, 0 variable 90 ubfx \tmp1, \tmp1, #4, #12 variable 92 cmp \tmp1, \tmp2 variable 96 .macro exit_smp, tmp1, tmp2 variable 97 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR variable 98 bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW variable 99 mcr p15, 0, \tmp1, c variable 102 check_cpu_part_num 0xc09, \\tmp1, \\tmp2 variable 103 mrceq p15, 0, \\tmp1, c0, c0, 5 variable 104 andeq \\tmp1, \\tmp1, #0xF variable 105 moveq \\tmp1, \\tmp1, lsl #2 variable 108 ldreq \\tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC) variable 117 mov32 \\tmp1, \\base variable 118 ldr \\tmp1, [\\tmp1, #APB_MISC_GP_HIDREV] variable 119 and \\tmp1, \\tmp1, #0xff00 variable 120 mov \\tmp1, \\tmp1, lsr #8 variable [all...] |
/arch/arm/mach-iop32x/include/mach/ |
H A D | entry-macro.S | 28 .macro arch_ret_to_user, tmp1, tmp2 29 mrc p15, 0, \tmp1, c15, c1, 0 30 ands \tmp2, \tmp1, #(1 << 6) 31 bicne \tmp1, \tmp1, #(1 << 6) 32 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
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/arch/arm64/lib/ |
H A D | strlen.S | 48 tmp1 .req x7 label 62 ands tmp1, srcin, #15 78 sub tmp1, data1, zeroones 82 bic has_nul1, tmp1, tmp2 100 CPU_BE( sub tmp1, data2, zeroones ) 102 CPU_BE( bic has_nul2, tmp1, tmp2 ) 111 cmp tmp1, #8 112 neg tmp1, tmp1 114 lsl tmp1, tmp [all...] |
H A D | strcmp.S | 57 tmp1 .req x7 label 64 eor tmp1, src1, src2 66 tst tmp1, #7 68 ands tmp1, src1, #7 80 sub tmp1, data1, zeroones 83 bic has_nul, tmp1, tmp2 /* Non-zero if NUL terminator. */ 96 lsl tmp1, tmp1, #3 /* Bytes beyond alignment -> bits. */ 98 neg tmp1, tmp1 /* Bit [all...] |
H A D | memcmp.S | 54 tmp1 .req x8 label 63 eor tmp1, src1, src2 64 tst tmp1, #7 66 ands tmp1, src1, #7 114 * We can not add limit with alignment offset(tmp1) here. Since the 120 add tmp3, tmp3, tmp1 122 add limit, limit, tmp1/* Adjust the limit for the extra. */ 124 lsl tmp1, tmp1, #3/* Bytes beyond alignment -> bits.*/ 125 neg tmp1, tmp [all...] |
H A D | strnlen.S | 50 tmp1 .req x8 label 66 ands tmp1, srcin, #15 86 sub tmp1, data1, zeroones 90 bic has_nul1, tmp1, tmp2 93 orr tmp1, has_nul1, has_nul2 94 ccmp tmp1, #0, #0, pl /* NZCV = 0000 */ 97 cbz tmp1, .Lhit_limit /* No null in final Qword. */ 118 CPU_BE( sub tmp1, data2, zeroones ) 120 CPU_BE( bic has_nul2, tmp1, tmp2 ) 136 * limit + tmp1 [all...] |
H A D | strncmp.S | 58 tmp1 .req x8 label 69 eor tmp1, src1, src2 71 tst tmp1, #7 73 ands tmp1, src1, #7 93 sub tmp1, data1, zeroones 97 bics has_nul, tmp1, tmp2 /* Non-zero if NUL terminator. */ 133 neg tmp3, tmp1, lsl #3 /* 64 - bits(bytes beyond align). */ 138 CPU_BE( lsl tmp2, tmp2, tmp3 ) /* Shift (tmp1 & 63). */ 140 CPU_LE( lsr tmp2, tmp2, tmp3 ) /* Shift (tmp1 & 63). */ 145 add limit, limit, tmp1 [all...] |
/arch/arm/mach-iop13xx/include/mach/ |
H A D | entry-macro.S | 37 .macro arch_ret_to_user, tmp1, tmp2 38 mrc p15, 0, \tmp1, c15, c1, 0 39 ands \tmp2, \tmp1, #(1 << 6) 40 bicne \tmp1, \tmp1, #(1 << 6) 41 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
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/arch/arm/mach-iop33x/include/mach/ |
H A D | entry-macro.S | 29 .macro arch_ret_to_user, tmp1, tmp2 30 mrc p15, 0, \tmp1, c15, c1, 0 31 ands \tmp2, \tmp1, #(1 << 6) 32 bicne \tmp1, \tmp1, #(1 << 6) 33 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
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/arch/m32r/include/asm/ |
H A D | spinlock.h | 43 unsigned long tmp1, tmp2; local 62 : "=&r" (oldval), "=&r" (tmp1), "=&r" (tmp2) 75 unsigned long tmp0, tmp1; local 106 : "=&r" (tmp0), "=&r" (tmp1) 154 unsigned long tmp0, tmp1; local 194 : "=&r" (tmp0), "=&r" (tmp1) 205 unsigned long tmp0, tmp1, tmp2; local 247 : "=&r" (tmp0), "=&r" (tmp1), "=&r" (tmp2) 258 unsigned long tmp0, tmp1; local 269 : "=&r" (tmp0), "=&r" (tmp1) 280 unsigned long tmp0, tmp1, tmp2; local [all...] |
/arch/m68k/lib/ |
H A D | checksum.c | 44 unsigned long tmp1, tmp2; local 62 "movel %1,%3\n\t" /* save len in tmp1 */ 90 "movel %3,%1\n\t" /* restore len from tmp1 */ 122 "=&d" (tmp1), "=&d" (tmp2) 144 unsigned long tmp1, tmp2; local 162 "movel %1,%4\n\t" /* save len in tmp1 */ 206 "movel %4,%1\n\t" /* restore len from tmp1 */ 314 "=&d" (tmp1), "=d" (tmp2) 333 unsigned long tmp1, tmp2; local 349 "movel %1,%4\n\t" /* save len in tmp1 */ [all...] |
/arch/s390/lib/ |
H A D | uaccess.c | 38 unsigned long tmp1, tmp2; local 40 tmp1 = -4096UL; 69 : "+a" (size), "+a" (ptr), "+a" (x), "+a" (tmp1), "=a" (tmp2) 77 unsigned long tmp1, tmp2; local 80 tmp1 = -256UL; 114 : "+a" (size), "+a" (ptr), "+a" (x), "+a" (tmp1), "=a" (tmp2) 131 unsigned long tmp1, tmp2; local 133 tmp1 = -4096UL; 152 : "+a" (size), "+a" (ptr), "+a" (x), "+a" (tmp1), "=a" (tmp2) 160 unsigned long tmp1, tmp local 204 unsigned long tmp1, tmp2; local 226 unsigned long tmp1; local 266 unsigned long tmp1, tmp2; local 293 unsigned long tmp1, tmp2; local 339 unsigned long tmp1, tmp2; local [all...] |
/arch/arm/include/asm/ |
H A D | tls.h | 9 .macro switch_tls_none, base, tp, tpuser, tmp1, tmp2 variable 12 .macro switch_tls_v6k, base, tp, tpuser, tmp1, tmp2 variable 19 .macro switch_tls_v6, base, tp, tpuser, tmp1, tmp2 variable 20 ldr \tmp1, =elf_hwcap variable 21 ldr \tmp1, [\tmp1, #0] 23 tst \tmp1, #HWCAP_TLS @ hardware TLS available? variable 31 .macro switch_tls_software, base, tp, tpuser, tmp1, tmp2 variable 32 mov \tmp1, #0xffff0fff variable 33 str \tp, [\tmp1, # [all...] |
/arch/hexagon/mm/ |
H A D | strnlen_user.S | 25 #define tmp1 r3 define 60 tmp1 = memb(start++#1); define 63 P0 = cmp.eq(tmp1,#0); 87 tmp1 = P0; define 91 tmp1 = ct0(tmp1); define 96 P0 = cmp.eq(tmp1,#32); 98 if (!P0.new) start = add(obo,tmp1); 108 P0 = cmp.gt(tmp1,mod8); 110 start = add(obo,tmp1); [all...] |
/arch/ia64/lib/ |
H A D | do_csum.S | 104 #define tmp1 r26 define 135 add tmp1=buf,len // last byte's address 148 adds tmp2=-1,tmp1 // last-1 149 and lastoff=7,tmp1 // how many bytes off for last element 151 sub tmp1=8,lastoff // complement to lastoff 160 and tmp1=7, tmp1 // make sure that if tmp1==8 -> tmp1=0 164 shl tmp1 [all...] |
/arch/tile/include/asm/ |
H A D | irqflags.h | 221 #define IRQ_DISABLE(tmp0, tmp1) \ 233 #define IRQ_ENABLE_LOAD(tmp0, tmp1) \ 236 #define IRQ_ENABLE_APPLY(tmp0, tmp1) \ 262 #define IRQ_DISABLE(tmp0, tmp1) \ 265 moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS_HI) \ 269 auli tmp1, tmp1, ha16(LINUX_MASKABLE_INTERRUPTS_HI) \ 271 mtspr SPR_INTERRUPT_MASK_SET_K_1, tmp1 280 #define IRQ_ENABLE_LOAD(tmp0, tmp1) \ 284 addi tmp1, tmp [all...] |
/arch/tile/lib/ |
H A D | memcpy_64.c | 99 op_t tmp0 = 0, tmp1 = 0, tmp2, tmp3; local 117 tmp1 = LD8(src8++); 133 tmp1 = LD8(src8++); 140 tmp0 = __insn_dblalign(tmp0, tmp1, srci); 144 tmp1 = __insn_dblalign(tmp1, tmp2, srci); 145 ST8(dst8++, tmp1); 151 tmp1 = LD8(src8++); 158 tmp0 = __insn_dblalign(tmp0, tmp1, srci); 183 tmp1 250 op_t tmp0, tmp1, tmp2, tmp3; local [all...] |
/arch/arc/include/asm/ |
H A D | uaccess.h | 170 unsigned long tmp1, tmp2, tmp3, tmp4; local 245 "=r"(tmp1), "=r"(tmp2), "=r"(tmp3), "=r"(tmp4) 269 "=r"(tmp1), "=r"(tmp2) 289 : "+r" (res), "+r"(to), "+r"(from), "=r"(tmp1) 309 : "+r" (res), "+r"(to), "+r"(from), "=r"(tmp1) 327 : "+r" (res), "+r"(to), "+r"(from), "=r"(tmp1) 384 "=r"(tmp1), "=r"(tmp2), "=r"(tmp3), "=r"(tmp4) 400 unsigned long tmp1, tmp2, tmp3, tmp4; local 470 "=r"(tmp1), "=r"(tmp2), "=r"(tmp3), "=r"(tmp4) 494 "=r"(tmp1), " 694 long res, tmp1, cnt; local [all...] |
/arch/alpha/lib/ |
H A D | divide.S | 56 #define tmp1 $3 define 108 stq tmp1,24($30) 140 subq modulus,divisor,tmp1 143 cmovne compare,tmp1,modulus 149 ldq tmp1,24($30) 181 stq tmp1,24($30) 188 subq $31,$27,tmp1 191 cmovlt $28,tmp1,$27 192 ldq tmp1,24($30)
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/arch/sh/lib/ |
H A D | io.c | 69 int tmp1; local 77 : "=&r" (data), "=&r" (tmp1)
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/arch/mips/mm/ |
H A D | sc-ip22.c | 88 unsigned long addr, tmp1, tmp2; local 114 : "=r" (tmp1), "=r" (tmp2), "=r" (addr)); 119 unsigned long tmp1, tmp2, tmp3; local 144 : "=r" (tmp1), "=r" (tmp2), "=r" (tmp3));
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