Searched refs:ul (Results 1 - 25 of 69) sorted by relevance

123

/arch/sh/include/mach-common/mach/
H A Dmicrodev.h26 #define MICRODEV_FPGA_INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */
27 #define MICRODEV_FPGA_INTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */
28 #define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interrupt mask to enable/disable INTC in CPU-board FPGA */
/arch/metag/include/asm/
H A Ddelay.h26 ((n) > 20000 ? __bad_ndelay() : __const_udelay((n) * 5ul)) : \
/arch/mips/include/asm/octeon/
H A Dpci-octeon.h53 #define OCTEON_PCI_BAR1_HOLE_SIZE (1ul<<(OCTEON_PCI_BAR1_HOLE_BITS+3))
/arch/powerpc/kvm/
H A Dbook3s_hv_builtin.c55 case 32ul << 20: /* 32 MB */
59 case 64ul << 20: /* 64 MB */
61 case 128ul << 20: /* 128 MB */
63 case 256ul << 20: /* 256 MB */
65 case 1ul << 30: /* 1 GB */
67 case 16ul << 30: /* 16 GB */
69 case 256ul << 30: /* 256 GB */
H A Dbook3s_hv_ras.c18 #define SRR1_MC_LDSTERR (1ul << (63-42))
/arch/alpha/lib/
H A Dchecksum.c23 unsigned long ul; member in union:__anon119
28 in_v.ul = x;
29 tmp_v.ul = (unsigned long) in_v.ui[0] + (unsigned long) in_v.ui[1];
33 out_v.ul = (unsigned long) tmp_v.us[0] + (unsigned long) tmp_v.us[1]
H A Dcsum_partial_copy.c79 unsigned long ul; member in union:__anon120
84 in_v.ul = x;
85 tmp_v.ul = (unsigned long) in_v.ui[0] + (unsigned long) in_v.ui[1];
89 out_v.ul = (unsigned long) tmp_v.us[0] + (unsigned long) tmp_v.us[1]
/arch/mips/kernel/
H A Djump_label.c37 #define J_RANGE_MASK ((1ul << (26 + J_RANGE_SHIFT)) - 1)
38 #define J_ALIGN_MASK ((1ul << J_RANGE_SHIFT) - 1)
H A Dcevt-r4k.c92 return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
/arch/m32r/mm/
H A Ddiscontig.c42 unsigned long ul; local
57 ul = zone_alignment;
58 while (start_pfn >= ul)
59 ul += zone_alignment;
61 start_pfn = ul - zone_alignment;
/arch/powerpc/mm/
H A Dslice.c64 *(p++) = (mask.high_slices & (1ul << i)) ? '1' : '0';
94 ret.high_slices = (1ul << (GET_HIGH_SLICE_INDEX(end) + 1))
95 - (1ul << GET_HIGH_SLICE_INDEX(start));
114 1ul << SLICE_LOW_SHIFT);
120 unsigned long end = start + (1ul << SLICE_HIGH_SHIFT);
145 ret.high_slices |= 1ul << i;
168 ret.high_slices |= 1ul << i;
225 if (mask.high_slices & (1ul << i))
261 return !!(available.high_slices & (1ul << slice));
276 info.align_mask = PAGE_MASK & ((1ul << pshif
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/arch/powerpc/include/asm/
H A Dkvm_book3s_64.h57 #define HPTE_GR_MODIFIED (1ul << 62)
189 rb &= ~((1ul << mmu_psize_defs[a_psize].shift) - 1);
218 return 1ul << 12;
228 return 1ul << mmu_psize_defs[size].shift;
229 return 1ul << mmu_psize_defs[a_psize].shift;
H A Dspu.h694 #define SPU_ECC_CORRECTED_ERROR (1ull << 0ul)
695 #define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul)
696 #define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul)
697 #define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul)
698 #define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul)
699 #define SPU_ECC_DATA_ERROR (1ull << 5ul)
700 #define SPU_ECC_DMA_ERROR (1ull << 6ul)
704 #define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul)
705 #define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul)
H A Dmmu-hash64.h279 return (pa & ~((1ul << shift) - 1)) | (penc << LP_SHIFT);
292 mask = (1ul << (s_shift - VPN_SHIFT)) - 1;
307 mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
311 mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
376 * For user processes max context id is limited to ((1ul << 19) - 5)
H A Dreg.h307 #define LPCR_VPM0 (1ul << (63-0))
308 #define LPCR_VPM1 (1ul << (63-1))
309 #define LPCR_ISL (1ul << (63-2))
312 #define LPCR_DPFD (7ul << LPCR_DPFD_SH)
314 #define LPCR_VRMA_L (1ul << (63-12))
315 #define LPCR_VRMA_LP0 (1ul << (63-15))
316 #define LPCR_VRMA_LP1 (1ul << (63-16))
347 #define PCR_VEC_DIS (1ul << (63-0)) /* Vec. disable (bit NA since POWER8) */
348 #define PCR_VSX_DIS (1ul << (63-1)) /* VSX disable (bit NA since POWER8) */
349 #define PCR_TM_DIS (1ul << (6
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/arch/mips/include/asm/
H A Dbitops.h512 if (!(word & (~0ul << 32))) {
517 if (!(word & (~0ul << (BITS_PER_LONG-16)))) {
521 if (!(word & (~0ul << (BITS_PER_LONG-8)))) {
525 if (!(word & (~0ul << (BITS_PER_LONG-4)))) {
529 if (!(word & (~0ul << (BITS_PER_LONG-2)))) {
533 if (!(word & (~0ul << (BITS_PER_LONG-1))))
/arch/arm/mm/
H A Dcache-xsc3l2.c102 if (start == 0 && end == -1ul) {
184 if (start == 0 && end == -1ul) {
H A Dmm.h90 #define arm_dma_pfn_limit (~0ul >> PAGE_SHIFT)
/arch/alpha/oprofile/
H A Dop_model_ev4.c41 ctl |= (ctr[1].enabled ? (ctr[1].event - 16) << 32 : 7ul << 32);
/arch/arm/mach-tegra/
H A Dirq.c177 writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
180 writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
199 writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
202 writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
/arch/mips/pci/
H A Dpci-octeon.c635 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30);
659 OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) -
662 octeon_pci_mem_resource.start + (1ul << 30);
665 octeon_npi_write32(CVMX_NPI_PCI_CFG04, 128ul << 20);
695 OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) +
696 (4ul << 10);
698 octeon_pci_mem_resource.start + (1ul << 30);
H A Dmsi-octeon.c151 ((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff;
152 msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32;
/arch/arm/mach-pxa/
H A Dclock-pxa3xx.c126 unsigned long mask = 1ul << (clk->cken & 0x1f);
138 unsigned long mask = 1ul << (clk->cken & 0x1f);
/arch/blackfin/include/asm/
H A Dipipe.h154 static inline unsigned long __ipipe_ffnz(unsigned long ul) argument
156 return ffs(ul) - 1;
/arch/sh/boards/mach-microdev/
H A Dirq.c128 __raw_writel(~0ul, MICRODEV_FPGA_INTDSB_REG);

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