/arch/mips/jz4740/ |
H A D | serial.c | 20 void jz4740_serial_out(struct uart_port *p, int offset, int value) argument 24 value |= 0x10; /* Enable uart module */ 27 value |= (value & 0x4) << 2; 32 writeb(value, p->membase + (offset << p->regshift));
|
H A D | serial.h | 21 void jz4740_serial_out(struct uart_port *p, int offset, int value);
|
/arch/metag/include/asm/ |
H A D | core_reg.h | 21 #define __core_reg_set(reg, value) do { \ 22 unsigned int __srvalue = (value); \ 28 #define __core_reg_swap(reg, value) do { \ 29 unsigned int __srvalue = (value); \ 32 (value) = __srvalue; \
|
/arch/avr32/mach-at32ap/ |
H A D | hmatrix.c | 16 static inline void __hmatrix_write_reg(unsigned long offset, u32 value) argument 18 __raw_writel(value, (void __iomem __force *)(HMATRIX_BASE + offset)); 29 * @value: value to be written to the register at @offset 31 void hmatrix_write_reg(unsigned long offset, u32 value) argument 34 __hmatrix_write_reg(offset, value); 43 * Returns the value of the register at @offset. 47 u32 value; local 50 value = __hmatrix_read_reg(offset); 53 return value; 63 u32 value; local 68 __hmatrix_write_reg(HMATRIX_SFR(slave_id), value); local 80 u32 value; local 85 __hmatrix_write_reg(HMATRIX_SFR(slave_id), value); local [all...] |
/arch/x86/include/asm/ |
H A D | debugreg.h | 16 #define set_debugreg(value, register) \ 17 native_set_debugreg(register, value) 49 static inline void native_set_debugreg(int regno, unsigned long value) argument 53 asm("mov %0, %%db0" ::"r" (value)); 56 asm("mov %0, %%db1" ::"r" (value)); 59 asm("mov %0, %%db2" ::"r" (value)); 62 asm("mov %0, %%db3" ::"r" (value)); 65 asm("mov %0, %%db6" ::"r" (value)); 68 asm("mov %0, %%db7" ::"r" (value));
|
H A D | xcr.h | 37 static inline void xsetbv(u32 index, u64 value) argument 39 u32 eax = value; 40 u32 edx = value >> 32;
|
/arch/mips/include/asm/octeon/ |
H A D | cvmx-fau.h | 57 * bit will be set. Otherwise the value of the register before 62 int64_t value:63; member in struct:__anon2014 67 * bit will be set. Otherwise the value of the register before 72 int32_t value:31; member in struct:__anon2015 77 * bit will be set. Otherwise the value of the register before 82 int16_t value:15; member in struct:__anon2016 87 * bit will be set. Otherwise the value of the register before 92 int8_t value:7; member in struct:__anon2017 97 * the error bit will be set. Otherwise the value of the 111 * @noadd: 0 = Store value i 142 __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg, int64_t value) argument 160 cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value) argument 175 cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value) argument 189 cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value) argument 202 cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) argument 220 cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value) argument 244 cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value) argument 267 cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value) argument 289 cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) argument 321 __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value, uint64_t tagwait, cvmx_fau_op_size_t size, uint64_t reg) argument 347 cvmx_fau_async_fetch_and_add64(uint64_t scraddr, cvmx_fau_reg_64_t reg, int64_t value) argument 367 cvmx_fau_async_fetch_and_add32(uint64_t scraddr, cvmx_fau_reg_32_t reg, int32_t value) argument 386 cvmx_fau_async_fetch_and_add16(uint64_t scraddr, cvmx_fau_reg_16_t reg, int16_t value) argument 404 cvmx_fau_async_fetch_and_add8(uint64_t scraddr, cvmx_fau_reg_8_t reg, int8_t value) argument 427 cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr, cvmx_fau_reg_64_t reg, int64_t value) argument 450 cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr, cvmx_fau_reg_32_t reg, int32_t value) argument 473 cvmx_fau_async_tagwait_fetch_and_add16(uint64_t scraddr, cvmx_fau_reg_16_t reg, int16_t value) argument 495 cvmx_fau_async_tagwait_fetch_and_add8(uint64_t scraddr, cvmx_fau_reg_8_t reg, int8_t value) argument 510 cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value) argument 522 cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value) argument 534 cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value) argument 545 cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value) argument 557 cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value) argument 569 cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value) argument 581 cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value) argument 592 cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value) argument [all...] |
H A D | cvmx-scratch.h | 45 * Reads an 8 bit value from the processor local scratchpad memory. 49 * Returns value read 57 * Reads a 16 bit value from the processor local scratchpad memory. 61 * Returns value read 69 * Reads a 32 bit value from the processor local scratchpad memory. 73 * Returns value read 81 * Reads a 64 bit value from the processor local scratchpad memory. 85 * Returns value read 93 * Writes an 8 bit value to the processor local scratchpad memory. 96 * @value 98 cvmx_scratch_write8(uint64_t address, uint64_t value) argument 110 cvmx_scratch_write16(uint64_t address, uint64_t value) argument 122 cvmx_scratch_write32(uint64_t address, uint64_t value) argument 134 cvmx_scratch_write64(uint64_t address, uint64_t value) argument [all...] |
/arch/sh/boards/ |
H A D | board-apsh4ad0a.c | 76 int value = 0; local 82 value |= MODE_PIN0; /* Clock Mode 3 */ 83 value |= MODE_PIN1; 84 value &= ~MODE_PIN2; 85 value &= ~MODE_PIN3; 86 value &= ~MODE_PIN4; /* 16-bit Area0 bus width */ 87 value |= MODE_PIN5; 88 value |= MODE_PIN6; 89 value |= MODE_PIN7; /* Normal mode */ 90 value | [all...] |
H A D | board-apsh4a3a.c | 151 int value = 0; local 157 value &= ~MODE_PIN0; /* Clock Mode 16 */ 158 value &= ~MODE_PIN1; 159 value &= ~MODE_PIN2; 160 value &= ~MODE_PIN3; 161 value |= MODE_PIN4; 162 value &= ~MODE_PIN5; /* 16-bit Area0 bus width */ 163 value |= MODE_PIN6; /* Area 0 SRAM interface */ 164 value |= MODE_PIN7; 165 value | [all...] |
/arch/arm/mach-at91/include/mach/ |
H A D | at91_matrix.h | 16 #define at91_matrix_write(field, value) \ 17 __raw_writel(value, at91_matrix_base + field)
|
/arch/m68k/include/asm/ |
H A D | movs.h | 10 /* Set DFC register value */ 15 /* Get DFC register value */ 20 /* Set SFC register value */ 25 /* Get SFC register value */ 38 #define SET_CONTROL_BYTE(addr,value) \ 39 __asm__ __volatile__ (" movsb %0, %1@" : : "d" (value), "a" (addr)); 43 #define GET_CONTROL_BYTE(addr,value) \ 44 __asm__ __volatile__ (" movsb %1@, %0" : "=d" (value) : "a" (addr)); 48 #define SET_CONTROL_WORD(addr,value) \ 49 __asm__ __volatile__ (" movsl %0, %1@" : : "d" (value), " [all...] |
/arch/tile/kernel/ |
H A D | module.c | 93 * Validate that the high 16 bits of "value" is just the sign-extension of 96 static int validate_hw2_last(long value, struct module *me) argument 98 if (((value << 16) >> 16) != value) { 99 pr_warning("module %s: Out of range HW2_LAST value %#lx\n", 100 me->name, value); 107 * Validate that "value" isn't too big to hold in a JumpOff relocation. 109 static int validate_jumpoff(long value) argument 115 long f = get_JumpOff_X1(create_JumpOff_X1(value)); 118 return f == value; 132 unsigned long value; local [all...] |
/arch/microblaze/kernel/ |
H A D | module.c | 29 unsigned long int value; local 43 value = sym->st_value + rela[i].r_addend; 57 *location = value + old_value; 60 old_value, value); 62 *location = value; 71 value += old_value; 74 (value >> 16); 76 (value & 0xFFFF); 79 old_value, value); 87 value [all...] |
/arch/microblaze/lib/ |
H A D | memcpy.c | 63 unsigned value, buf_hold; local 100 value = *i_src++; 101 *i_dst++ = buf_hold | value >> 24; 102 buf_hold = value << 8; 109 value = *i_src++; 110 *i_dst++ = buf_hold | ((value & 0xFF) << 24); 111 buf_hold = (value & 0xFFFFFF00) >> 8; 126 value = *i_src++; 127 *i_dst++ = buf_hold | value >> 16; 128 buf_hold = value << 1 [all...] |
H A D | memmove.c | 84 unsigned value, buf_hold; local 122 value = *--i_src; 123 *--i_dst = buf_hold << 8 | value; 124 buf_hold = value >> 24; 131 value = *--i_src; 133 ((value & 0xFFFFFF00) >> 8); 134 buf_hold = (value & 0xFF) << 24; 149 value = *--i_src; 150 *--i_dst = buf_hold << 16 | value; 151 buf_hold = value >> 1 [all...] |
/arch/openrisc/kernel/ |
H A D | module.c | 30 uint32_t value; local 43 value = sym->st_value + rel[i].r_addend; 47 *location = value; 50 *((uint16_t *)location + 1) = value; 53 *((uint16_t *)location + 1) = value >> 16; 56 value -= (uint32_t)location; 57 value >>= 2; 58 value &= 0x03ffffff; 59 value |= *location & 0xfc000000; 60 *location = value; [all...] |
/arch/alpha/kernel/ |
H A D | module.c | 170 unsigned long value, hi, lo; local 179 value = sym->st_value + rela[i].r_addend; 186 ((u32 *)location)[0] = value; 187 ((u32 *)location)[1] = value >> 32; 190 value -= gp; 191 if ((int)value != value) 193 *(u32 *)location = value; 201 *(u64 *)hi = value; 206 value [all...] |
/arch/powerpc/xmon/ |
H A D | ppc-dis.c | 99 long value; local 109 /* Extract the value from the instruction. */ 111 value = (*operand->extract) (insn, dialect, &invalid); 114 value = (insn >> operand->shift) & ((1 << operand->bits) - 1); 116 && (value & (1 << (operand->bits - 1))) != 0) 117 value -= 1 << operand->bits; 120 /* If the operand is optional, and the value is zero, don't 124 && value == 0) 135 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0)) 136 printf("r%ld", value); [all...] |
/arch/xtensa/kernel/ |
H A D | module.c | 59 uint32_t value; local 70 value = sym->st_value + rela[i].r_addend; 82 *(uint32_t *)location += value; 87 value -= ((unsigned long)location & -4) + 4; 88 if ((value & 3) != 0 || 89 ((value + (1 << 19)) >> 20) != 0) { 97 value = (signed int)value >> 2; 100 ((value >> 16) & 0x3)); 101 location[1] = (value >> [all...] |
/arch/mips/kernel/ |
H A D | unaligned.c | 112 #define LoadHW(addr, value, res) \ 129 : "=&r" (value), "=r" (res) \ 132 #define LoadW(addr, value, res) \ 147 : "=&r" (value), "=r" (res) \ 150 #define LoadHWU(addr, value, res) \ 169 : "=&r" (value), "=r" (res) \ 172 #define LoadWU(addr, value, res) \ 189 : "=&r" (value), "=r" (res) \ 192 #define LoadDW(addr, value, res) \ 207 : "=&r" (value), " 429 unsigned long value; local 775 unsigned long value; local 1395 unsigned long value; local [all...] |
/arch/arm/kernel/ |
H A D | io.c | 17 u32 value; local 20 value = readl_relaxed(reg) & ~mask; 21 value |= (set & mask); 22 writel_relaxed(value, reg); 30 u32 value; local 33 value = readl_relaxed(reg) & ~mask; 34 value |= (set & mask); 35 writel(value, reg);
|
/arch/cris/include/asm/ |
H A D | etraxi2c.h | 13 * slave, register and value. 16 #define I2C_WRITEARG(slave, reg, value) (((slave) << 16) | ((reg) << 8) | (value))
|
/arch/mips/include/asm/mach-cavium-octeon/ |
H A D | gpio.h | 12 int gpio_direction_output(unsigned gpio, int value); 14 void gpio_set_value(unsigned gpio, int value);
|
/arch/mips/include/asm/mach-generic/ |
H A D | gpio.h | 12 int gpio_direction_output(unsigned gpio, int value); 14 void gpio_set_value(unsigned gpio, int value);
|