/arch/xtensa/include/asm/ |
H A D | tlbflush.h | 130 static inline void write_dtlb_entry (pte_t entry, int way) argument 133 : : "r" (way), "r" (entry) ); 136 static inline void write_itlb_entry (pte_t entry, int way) argument 139 : : "r" (way), "r" (entry) ); 179 static inline unsigned long read_dtlb_virtual (int way) argument 182 __asm__ __volatile__("rdtlb0 %0, %1\n\t" : "=a" (tmp), "+a" (way)); 186 static inline unsigned long read_dtlb_translation (int way) argument 189 __asm__ __volatile__("rdtlb1 %0, %1\n\t" : "=a" (tmp), "+a" (way)); 193 static inline unsigned long read_itlb_virtual (int way) argument 196 __asm__ __volatile__("ritlb0 %0, %1\n\t" : "=a" (tmp), "+a" (way)); 200 read_itlb_translation(int way) argument [all...] |
/arch/arm/mm/ |
H A D | cache-xsc3l2.c | 56 int set, way; local 61 for (way = 0; way < CACHE_WAY_PER_SET; way++) { 62 set_way = (way << 29) | (set << 5); 161 * optimize L2 flush all operation by set/way format 166 int set, way; local 171 for (way = 0; way < CACHE_WAY_PER_SET; way [all...] |
H A D | cache-v7.S | 144 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 145 clz r5, r4 @ find bit position of way size increment 151 ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11 153 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 157 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 160 subs r4, r4, #1 @ decrement the way
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H A D | proc-feroceon.S | 63 tst r0, #(1 << 16) @ get way 65 movne r3, #((4 - 1) << 30) @ 4-way 67 moveq r3, #0 @ 1-way 162 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way 163 subs ip, ip, #(1 << 30) @ next way 480 * lr to do so. The only way without touching main memory is to
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/arch/sh/mm/ |
H A D | cache-sh2a.c | 27 static void sh2a_flush_oc_line(unsigned long v, int way) argument 29 unsigned long addr = (v & 0x000007f0) | (way << 11); 77 int way; local 78 for (way = 0; way < nr_ways; way++) { 80 sh2a_flush_oc_line(v, way); 107 int way; local 109 for (way = 0; way < nr_way [all...] |
H A D | cache-sh2.c | 29 int way; local 30 for (way = 0; way < 4; way++) { 31 unsigned long data = __raw_readl(addr | (way << 12)); 34 __raw_writel(data, addr | (way << 12));
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H A D | cache-debugfs.c | 29 unsigned int waysize, way; local 66 for (way = 0; way < cache->ways; way++) { 71 seq_printf(file, "Way %d\n", way);
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/arch/arc/mm/ |
H A D | tlb.c | 63 * ARC700 MMU-v1 had a Joint-TLB for Code and Data and is 2 way set-assoc. 68 * Although J-TLB is 2 way set assoc, ARC700 caches J-TLB into uTLBS which has 241 * Flush the entrie MM for userland. The fastest way is to move to Next ASID 270 * -Here the fastest way (if range is too large) is to move to next ASID 670 #define SET_WAY_TO_IDX(mmu, set, way) ((set) * mmu->ways + (way)) 685 int set, way, n; local 699 for (way = 0, is_valid = 0; way < mmu->ways; way [all...] |
/arch/arc/include/asm/ |
H A D | tlb-mmu1.h | 23 ; Calculate set index for 2-way MMU 41 or.nz r0,r0,1 ; set way bit 48 ; Faster than hack #1 in non-thrash case, but hard-coded for 2-way MMU 55 and.f r0,r0,0x000fe000 /* 2-way MMU mask */
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/arch/mips/mm/ |
H A D | cerr-sb1.c | 334 unsigned short way; local 343 for (way = 0; way < 4; way++) { 357 : "r" ((way << 13) | addr)); 360 if (way == 0) { 390 way, va, valid, taghi, taglo); 412 : "r" ((way << 13) | addr | (offset << 3))); 490 int valid, way; local 498 for (way [all...] |
/arch/x86/boot/ |
H A D | code16gcc.h | 5 # This is done this way instead via asm() to make sure gcc does not reorder
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H A D | pmjump.S | 58 # The 32-bit code sets up its own stack, but this way we do have
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/arch/blackfin/mach-common/ |
H A D | pm.c | 106 register u32 way, bank, subbank, set; local 114 for (way = 0; way < 2; ++way) 119 way << 26 |
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/arch/mn10300/mm/ |
H A D | cache-inv-by-tag.S | 184 # process the way 0 slot 185 mov (L1_CACHE_WAYDISP*0,a0),d0 # read the tag in the way 0 slot 198 # process the way 1 slot 199 mov (L1_CACHE_WAYDISP*1,a0),d0 # read the tag in the way 1 slot 212 # process the way 2 slot 213 mov (L1_CACHE_WAYDISP*2,a0),d0 # read the tag in the way 2 slot 226 # process the way 3 slot 227 mov (L1_CACHE_WAYDISP*3,a0),d0 # read the tag in the way 3 slot
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/arch/x86/crypto/ |
H A D | Makefile | 21 obj-$(CONFIG_CRYPTO_TWOFISH_X86_64_3WAY) += twofish-x86_64-3way.o 61 twofish-x86_64-3way-y := twofish-x86_64-asm_64-3way.o twofish_glue_3way.o
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/arch/mips/cavium-octeon/executive/ |
H A D | cvmx-l2c.c | 317 uint64_t way; local 323 for (way = 0; way < assoc; way++) { 324 CVMX_CACHE_LTGL2I(index | (way << shift), 0); 333 if (way >= assoc) { 343 return way; 572 * @assoc: Association (way) of the tag to dump 814 * 0 0 16-way 2MB cache 815 * 0 1 12-way 1. [all...] |
/arch/mips/dec/ |
H A D | int-handler.S | 286 move a1,t0 # cheats way of printing an arg! 290 move a1,t0 # cheats way of printing an arg!
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/arch/cris/include/arch-v32/mach-a3/mach/hwregs/ |
H A D | l2cache_defs.h | 107 unsigned int way : 3; member in struct:__anon1131
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/arch/x86/kernel/ |
H A D | verify_cpu.S | 41 pushfl # standard way to check for cpuid
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/arch/openrisc/ |
H A D | Kconfig | 127 On some architectures there is currently no way for the boot loader
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/arch/ia64/include/asm/ |
H A D | pal.h | 289 way : 8, /* 23-16 way in the set member in struct:pal_cache_line_id_u::__anon1530 302 way : 8, /* 23-16 way in the set member in struct:pal_cache_line_id_u::__anon1531 325 #define pclid_read_way pclid_info_read.way 334 #define pclid_write_way pclid_info_write.way 504 way : 5, /* Way in which the member in struct:pal_cache_check_info_s 639 way : 6, /* Way of structure */ member in struct:pal_uarch_check_info_s 640 wv : 1, /* way valid */ 724 #define pmci_cache_way pme_cache.way [all...] |
/arch/c6x/ |
H A D | Kconfig | 65 On some architectures there is currently no way for the boot loader
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/arch/alpha/lib/ |
H A D | ev6-memchr.S | 45 # the length is the easiest way to avoid trouble.
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H A D | memchr.S | 48 # the length is the easiest way to avoid trouble.
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/arch/mn10300/kernel/ |
H A D | switch_to.S | 91 # Clear the single-step flag to prevent us coming this way until we get
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