/drivers/staging/vt6655/ |
H A D | hostap.h | 41 #define WLAN_RATE_18M BIT7
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H A D | 80211hdr.h | 44 #define BIT7 0x00000080 macro 160 #define WLAN_GET_FC_FSTYPE(n) ((((unsigned short)(n) >> 8) & (BIT4|BIT5|BIT6|BIT7)) >> 4) 182 #define WLAN_GET_CAP_INFO_AGILITY(n) ((((n) >> 8) & BIT7) >> 7) 193 #define WLAN_GET_FC_FSTYPE(n) ((((unsigned short)(n)) & (BIT4|BIT5|BIT6|BIT7)) >> 4) 215 #define WLAN_GET_CAP_INFO_AGILITY(n) (((n) & BIT7) >> 7) 262 #define WLAN_MGMT_IS_BASICRATE(b) ((b) & BIT7) 263 #define WLAN_MGMT_GET_RATE(b) ((b) & ~BIT7)
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H A D | ioctl.c | 522 pMgmt->abyIBSSSuppRates[2] |= BIT7; 523 pMgmt->abyIBSSSuppRates[3] |= BIT7; 524 pMgmt->abyIBSSSuppRates[4] |= BIT7; 525 pMgmt->abyIBSSSuppRates[5] |= BIT7; 527 pMgmt->abyIBSSSuppRates[2] |= BIT7; 528 pMgmt->abyIBSSSuppRates[3] |= BIT7; 529 pMgmt->abyIBSSSuppRates[4] |= BIT7; 531 pMgmt->abyIBSSSuppRates[2] |= BIT7; 532 pMgmt->abyIBSSSuppRates[3] |= BIT7; 534 pMgmt->abyIBSSSuppRates[2] |= BIT7; [all...] |
/drivers/staging/rtl8188eu/include/ |
H A D | pwrseq.h | 74 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, \ 77 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, \ 129 PWR_CMD_WRITE, 0xFF, BIT7}, \ 169 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, \ 219 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, \ 229 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, \ 286 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, [all...] |
H A D | odm_debug.h | 67 #define ODM_COMP_PWR_SAVE BIT7
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H A D | rtl8188e_spec.h | 33 #define BIT7 0x00000080 macro 507 #define HSIMR_PDN_INT_EN BIT7 514 #define HSISR_PDNINT BIT7 547 #define CMD_IOCONFIG_ERR BIT7 558 #define RRSR_18M BIT7 635 #define IMR_HIGHDOK_88E BIT7 /* High Queue DMA OK */ 723 #define RCR_CBSSID_BCN BIT7 /* Accept BSSID match packet 1207 #define SDIO_HIMR_TXBCNERR_MSK BIT7 1233 #define SDIO_HISR_TXBCNERR BIT7
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H A D | odm.h | 424 ODM_BB_PWR_SAVE = BIT7, 470 ODM_RF_RX_D = BIT7, 508 ODM_WIFI_DIRECT = BIT7,
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H A D | osdep_service.h | 114 #define BIT7 0x00000080 macro
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/drivers/net/wireless/rtlwifi/btcoexist/ |
H A D | halbt_precomp.h | 55 #define BIT7 0x00000080 macro
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H A D | halbtc8723b2ant.h | 33 #define BT_INFO_8723B_2ANT_B_FTP BIT7
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H A D | halbtc8821a2ant.h | 30 #define BT_INFO_8821A_2ANT_B_FTP BIT7
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H A D | halbtc8192e2ant.h | 30 #define BT_INFO_8192E_2ANT_B_FTP BIT7
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H A D | halbtc8723b1ant.h | 30 #define BT_INFO_8723B_1ANT_B_FTP BIT7
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H A D | halbtc8821a1ant.h | 32 #define BT_INFO_8821A_1ANT_B_FTP BIT7
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/drivers/video/fbdev/via/ |
H A D | via_utility.c | 152 viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7); 162 viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7); 207 viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7); 217 viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7);
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H A D | lcd.c | 390 viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6); 402 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7); 625 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7); 634 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7); 641 viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7); 653 viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7); 677 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7); 686 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7); 696 viafb_write_reg_mask(CRD2, VIACR, 0, BIT7); 708 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7); [all...] |
H A D | dvi.c | 69 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7); 76 BIT5 + BIT6 + BIT7); 467 viafb_write_reg_mask(CR91, VIACR, 0, BIT7);
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H A D | hw.c | 481 viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7); 486 viafb_write_reg_mask(CR11, VIACR, 0, BIT7); 960 viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7); 1684 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6); 1691 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6); 2049 viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7); 2057 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
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H A D | share.h | 35 #define BIT7 0x80 macro
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/drivers/scsi/ |
H A D | tmscsim.h | 185 #define BIT7 0x00000080 macro 214 #define SRB_DISCONNECT BIT7 240 #define DATAOUT BIT7 364 #define DMA_COMMAND BIT7 390 #define INTERRUPT BIT7 399 #define SCSI_RESET BIT7 423 #define EXTENDED_TIMING BIT7 433 #define ID_MSG_CHECK BIT7 441 #define EATER_25NS BIT7 443 #define EATER_0NS (BIT7 [all...] |
H A D | dc395x.h | 68 #define BIT7 0x00000080 macro 136 #define DATAOUT BIT7
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/drivers/staging/rtl8188eu/hal/ |
H A D | odm_RTL8188E.c | 31 phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); 49 phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); 62 phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); 81 phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); 170 phy_set_bb_reg(adapter, 0x864, BIT8|BIT7|BIT6, 1); 174 phy_set_bb_reg(adapter, 0xc50, BIT7, 1); 210 BIT8|BIT7|BIT6, optional_ant); 214 BIT6|BIT7, default_ant); 219 BIT8|BIT7|BIT6, optional_ant); 347 phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, [all...] |
/drivers/net/wireless/rtlwifi/rtl8821ae/ |
H A D | pwrseq.h | 54 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \ 115 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \ 174 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \ 235 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \ 240 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \ 304 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \ 307 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \ 423 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \ 521 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, [all...] |
/drivers/staging/rtl8192e/rtl8192e/ |
H A D | r8192E_hw.h | 235 #define IMR_COMDOK BIT7 252 #define TPPoll_HQ BIT7 382 #define RRSR_18M BIT7
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/drivers/staging/rtl8192e/ |
H A D | rtl819x_Qos.h | 31 #define BIT7 0x00000080 macro
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