Searched refs:CSR1 (Results 1 - 16 of 16) sorted by relevance
| /drivers/net/wan/ |
| H A D | sbni.h | 27 CSR1 = 1, enumerator in enum:sbni_reg
43 /* CSR1 mapping */
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| H A D | sbni.c | 102 struct sbni_csr1 csr1; /* current value of CSR1 */
364 outb( PR_RES, ioaddr + CSR1 );
1056 dev->base_addr + CSR1 );
1100 outb( *(u_char *)&nl->csr1 | PR_RES, dev->base_addr + CSR1 );
1125 outb( *(u8 *)&nl->csr1, dev->base_addr + CSR1 );
1143 outb( *(unsigned char *)&nl->csr1, dev->base_addr + CSR1 );
1345 outb( *(u8 *)&nl->csr1 | PR_RES, dev->base_addr + CSR1 );
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| /drivers/staging/media/dt3155v4l/ |
| H A D | dt3155v4l.c | 206 pd->regs + CSR1);
331 tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD);
337 ipd->regs + CSR1);
370 FLD_DN_ODD | FLD_DN_EVEN, ipd->regs + CSR1);
737 pd->regs + CSR1);
742 iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
804 iowrite32(FIFO_EN | SRST | CAP_CONT_ODD, pd->regs + CSR1);
814 iowrite32(FIFO_EN | SRST | FLD_DN_EVEN | FLD_DN_ODD, pd->regs + CSR1);
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| H A D | dt3155v4l.h | 47 #define CSR1 0x40 macro
80 /* CSR1 bit masks */
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| /drivers/net/ethernet/dec/tulip/ |
| H A D | tulip.h | 107 CSR1 = 0x08, enumerator in enum:tulip_offsets
565 iowrite32(0, ioaddr + CSR1);
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| H A D | xircom_cb.c | 49 #define CSR1 0x08 macro
532 This is accomplished by writing to the CSR1 port. The documentation
540 xw32(CSR1, 0);
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| H A D | interrupt.c | 680 iowrite32(0, ioaddr + CSR1);
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| H A D | tulip_core.c | 708 iowrite32(0, tp->base_addr + CSR1);
1184 iowrite32(0, ioaddr + CSR1);
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| /drivers/net/ethernet/amd/ |
| H A D | ariadne.h | 63 #define CSR1 0x0100 /* - IADR[15:0] */ macro
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| H A D | atarilance.c | 304 #define CSR1 1 /* init block addr (low) */ macro
654 REGA( CSR1 ) = 0;
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| H A D | sun3lance.c | 203 #define CSR1 1 /* init block addr (low) */ macro
502 REGA(CSR1) = dvma_vtob(&(MEM->init));
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| H A D | ni65.c | 151 #define CSR1 0x01 macro
590 writereg(pib & 0xffff,CSR1);
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| /drivers/net/wireless/rt2x00/ |
| H A D | rt2400pci.c | 886 rt2x00mmio_register_read(rt2x00dev, CSR1, ®);
890 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
892 rt2x00mmio_register_read(rt2x00dev, CSR1, ®);
895 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
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| H A D | rt2400pci.h | 69 * CSR1: System control register.
74 #define CSR1 0x0004 macro
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| H A D | rt2500pci.c | 1024 rt2x00mmio_register_read(rt2x00dev, CSR1, ®);
1028 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
1030 rt2x00mmio_register_read(rt2x00dev, CSR1, ®);
1033 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
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| H A D | rt2500pci.h | 80 * CSR1: System control register.
85 #define CSR1 0x0004 macro
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