Searched refs:CSR3 (Results 1 - 15 of 15) sorted by relevance
/drivers/net/ethernet/amd/ |
H A D | am79c961a.h | 48 #define CSR3 3 macro
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H A D | sun3lance.c | 205 #define CSR3 3 /* misc */ macro 228 /* CSR3 */ 506 REGA(CSR3) = CSR3_BSWP | CSR3_ACON | CSR3_BCON; 508 REGA(CSR3) = CSR3_BSWP; 537 REGA(CSR3) = CSR3_BSWP; 718 REGA(CSR3) = CSR3_BSWP; 756 REGA(CSR3) = CSR3_BSWP; 929 REGA( CSR3 ) = CSR3_BSWP;
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H A D | am79c961a.c | 300 write_rreg (dev->base_addr, CSR3, CSR3_IDONM|CSR3_BABLM|CSR3_DXSUFLO); 369 write_rreg (dev->base_addr, CSR3, CSR3_MASKALL); 643 write_rreg (dev->base_addr, CSR3, CSR3_MASKALL);
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H A D | ariadne.h | 65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */ macro 198 * Bit definitions for CSR3 (Interrupt Masks and Deferral Control)
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H A D | atarilance.c | 306 #define CSR3 3 /* misc */ macro 329 /* CSR3 */ 652 REGA( CSR3 ) = CSR3_BSWP | (lp->cardtype == PAM_CARD ? CSR3_ACON : 0); 743 REGA( CSR3 ) = CSR3_BSWP | (lp->cardtype == PAM_CARD ? CSR3_ACON : 0); 1108 REGA( CSR3 ) = CSR3_BSWP | (lp->cardtype == PAM_CARD ? CSR3_ACON : 0);
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H A D | pcnet32.c | 206 #define CSR3 3 macro 463 val = lp->a->read_csr(ioaddr, CSR3); 465 lp->a->write_csr(ioaddr, CSR3, val); 1359 val = lp->a->read_csr(ioaddr, CSR3); 1361 lp->a->write_csr(ioaddr, CSR3, val); 2169 val = lp->a->read_csr(ioaddr, CSR3); 2171 lp->a->write_csr(ioaddr, CSR3, val); 2517 val = lp->a->read_csr(ioaddr, CSR3); 2519 lp->a->write_csr(ioaddr, CSR3, val);
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H A D | ni65.c | 153 #define CSR3 0x03 macro 588 writereg(0,CSR3); /* busmaster/no word-swap */
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H A D | ariadne.c | 427 lance->RAP = CSR3; /* Interrupt Masks and Deferral Control */
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/drivers/net/ethernet/dec/tulip/ |
H A D | tulip.h | 109 CSR3 = 0x18, enumerator in enum:tulip_offsets
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H A D | xircom_cb.c | 51 #define CSR3 0x18 macro 593 xw32(CSR3, address); /* Receive descr list address */ 631 xw32(CSR3, val); /* Receive descriptor address */
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H A D | tulip_core.c | 333 iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
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/drivers/net/wireless/rt2x00/ |
H A D | rt2400pci.h | 85 * CSR3: STA MAC address register 0. 87 #define CSR3 0x000c macro
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H A D | rt2500pci.h | 96 * CSR3: STA MAC address register 0. 98 #define CSR3 0x000c macro
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H A D | rt2400pci.c | 311 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
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H A D | rt2500pci.c | 317 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
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