Searched refs:CSR3 (Results 1 - 15 of 15) sorted by relevance

/drivers/net/ethernet/amd/
H A Dam79c961a.h48 #define CSR3 3 macro
H A Dsun3lance.c205 #define CSR3 3 /* misc */ macro
228 /* CSR3 */
506 REGA(CSR3) = CSR3_BSWP | CSR3_ACON | CSR3_BCON;
508 REGA(CSR3) = CSR3_BSWP;
537 REGA(CSR3) = CSR3_BSWP;
718 REGA(CSR3) = CSR3_BSWP;
756 REGA(CSR3) = CSR3_BSWP;
929 REGA( CSR3 ) = CSR3_BSWP;
H A Dam79c961a.c300 write_rreg (dev->base_addr, CSR3, CSR3_IDONM|CSR3_BABLM|CSR3_DXSUFLO);
369 write_rreg (dev->base_addr, CSR3, CSR3_MASKALL);
643 write_rreg (dev->base_addr, CSR3, CSR3_MASKALL);
H A Dariadne.h65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */ macro
198 * Bit definitions for CSR3 (Interrupt Masks and Deferral Control)
H A Datarilance.c306 #define CSR3 3 /* misc */ macro
329 /* CSR3 */
652 REGA( CSR3 ) = CSR3_BSWP | (lp->cardtype == PAM_CARD ? CSR3_ACON : 0);
743 REGA( CSR3 ) = CSR3_BSWP | (lp->cardtype == PAM_CARD ? CSR3_ACON : 0);
1108 REGA( CSR3 ) = CSR3_BSWP | (lp->cardtype == PAM_CARD ? CSR3_ACON : 0);
H A Dpcnet32.c206 #define CSR3 3 macro
463 val = lp->a->read_csr(ioaddr, CSR3);
465 lp->a->write_csr(ioaddr, CSR3, val);
1359 val = lp->a->read_csr(ioaddr, CSR3);
1361 lp->a->write_csr(ioaddr, CSR3, val);
2169 val = lp->a->read_csr(ioaddr, CSR3);
2171 lp->a->write_csr(ioaddr, CSR3, val);
2517 val = lp->a->read_csr(ioaddr, CSR3);
2519 lp->a->write_csr(ioaddr, CSR3, val);
H A Dni65.c153 #define CSR3 0x03 macro
588 writereg(0,CSR3); /* busmaster/no word-swap */
H A Dariadne.c427 lance->RAP = CSR3; /* Interrupt Masks and Deferral Control */
/drivers/net/ethernet/dec/tulip/
H A Dtulip.h109 CSR3 = 0x18, enumerator in enum:tulip_offsets
H A Dxircom_cb.c51 #define CSR3 0x18 macro
593 xw32(CSR3, address); /* Receive descr list address */
631 xw32(CSR3, val); /* Receive descriptor address */
H A Dtulip_core.c333 iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
/drivers/net/wireless/rt2x00/
H A Drt2400pci.h85 * CSR3: STA MAC address register 0.
87 #define CSR3 0x000c macro
H A Drt2500pci.h96 * CSR3: STA MAC address register 0.
98 #define CSR3 0x000c macro
H A Drt2400pci.c311 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
H A Drt2500pci.c317 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,

Completed in 787 milliseconds