Searched refs:ENABLE (Results 1 - 25 of 25) sorted by relevance

/drivers/staging/media/davinci_vpfe/
H A Ddm365_resizer.h170 #define ENABLE 1 macro
171 #define DISABLE (!ENABLE)
H A Ddm365_resizer.c123 param->rsz_en[RSZ_A] = ENABLE;
153 param->rsz_en[index] = ENABLE;
340 resizer_enable_422_420_conversion(param, RSZ_A, ENABLE);
503 param->rsz_en[RSZ_A] = ENABLE;
512 param->rsz_en[RSZ_B] = ENABLE;
524 RSZ_B, ENABLE);
702 param->rsz_en[RSZ_A] = ENABLE;
719 RSZ_A, ENABLE);
726 param->rsz_en[RSZ_B] = ENABLE;
737 RSZ_B, ENABLE);
[all...]
/drivers/net/wireless/ti/wl1251/
H A Dreg.h62 #define ENABLE (REGISTERS_BASE + 0x5450) macro
291 #define REG_ENABLE_TX_RX (ENABLE)
H A Dboot.c64 wl1251_reg_write32(wl, ENABLE, 0x0);
/drivers/scsi/aic7xxx/
H A Daic7770.c257 ahc_outb(ahc, BCTL, ENABLE);
267 ahc_outb(ahc, BCTL, ENABLE);
H A Daic7xxx.reg740 field ENABLE 0x01
H A Daic7xxx_reg.h_shipped590 #define ENABLE 0x01
/drivers/net/plip/
H A Dplip.c128 #define ENABLE(irq) if (irq != -1) enable_irq(irq) macro
612 ENABLE(dev->irq);
686 ENABLE(dev->irq);
692 ENABLE(dev->irq);
790 ENABLE(dev->irq);
854 ENABLE(dev->irq);
892 ENABLE(dev->irq);
/drivers/char/
H A Ddsp56k.c60 #define handshake(count, maxio, timeout, ENABLE, f) \
66 for (t = 0; t < timeout && !ENABLE; t++) \
68 if(!ENABLE) \
/drivers/gpu/drm/radeon/
H A Drv6xxd.h197 # define ENABLE (1 << 0) macro
H A Dnid.h707 #define ENABLE (1 << 0) macro
/drivers/input/serio/
H A Dgscps2.c52 #define ENABLE 1 macro
308 gscps2_enable(ps2port, ENABLE);
/drivers/video/fbdev/
H A Dstifb.c176 #define ENABLE 1 /* for enabling/disabling screen */ macro
764 case ENABLE:
982 int enable = (blank_mode == 0) ? ENABLE : DISABLE;
1027 hyperResetPlanes(fb, ENABLE);
/drivers/net/ethernet/broadcom/
H A Dsb1250-mac.c348 #define ENABLE 1 macro
1162 if (sc->rx_hw_checksum == ENABLE) {
1757 sc->rx_hw_checksum = ENABLE;
2287 if (sc->rx_hw_checksum == ENABLE)
/drivers/pci/hotplug/
H A Dibmphp_core.c583 case ENABLE:
1026 rc = validate(slot_cur, ENABLE);
H A Dibmphp.h679 #define ENABLE 1 macro
/drivers/scsi/isci/
H A Dregisters.h561 (SCU_UFQGP_GEN_BIT(ENABLE) | value)
564 (~SCU_UFQGP_GEN_BIT(ENABLE) & value)
H A Dphy.c530 enable_spinup |= SCU_ENSPINUP_GEN_BIT(ENABLE);
1196 enable_spinup_value &= ~SCU_ENSPINUP_GEN_BIT(ENABLE);
H A Dport.c1444 pts_control_value |= SCU_PTSxCR_GEN_BIT(ENABLE) | SCU_PTSxCR_GEN_BIT(SUSPEND);
1454 ~(SCU_PTSxCR_GEN_BIT(ENABLE) | SCU_PTSxCR_GEN_BIT(SUSPEND));
H A Dhost.c562 SMU_CQGR_GEN_BIT(ENABLE) |
772 | (SMU_CQGR_GEN_BIT(ENABLE))
/drivers/regulator/
H A Dlp8788-ldo.c88 #define ENABLE GPIOF_OUT_INIT_HIGH macro
/drivers/net/ethernet/chelsio/cxgb4/
H A Dt4_regs.h440 #define ENABLE (1U << 30) macro
H A Dt4_hw.c152 u32 req = ENABLE | FUNCTION(adap->fn) | reg;
160 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
162 * ENABLE is 0 so a simple register write is easier than a
/drivers/pinctrl/
H A Dpinctrl-palmas.c337 FUNCTION_GROUP(enable, ENABLE)
/drivers/gpu/drm/nouveau/core/engine/graph/
H A Dctxnv50.c182 cp_set (ctx, XFER_SWITCH, ENABLE);
962 dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_PTSZ.ENABLE */

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