Searched refs:ENABLE (Results 1 - 25 of 25) sorted by relevance
/drivers/staging/media/davinci_vpfe/ |
H A D | dm365_resizer.h | 170 #define ENABLE 1 macro 171 #define DISABLE (!ENABLE)
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H A D | dm365_resizer.c | 123 param->rsz_en[RSZ_A] = ENABLE; 153 param->rsz_en[index] = ENABLE; 340 resizer_enable_422_420_conversion(param, RSZ_A, ENABLE); 503 param->rsz_en[RSZ_A] = ENABLE; 512 param->rsz_en[RSZ_B] = ENABLE; 524 RSZ_B, ENABLE); 702 param->rsz_en[RSZ_A] = ENABLE; 719 RSZ_A, ENABLE); 726 param->rsz_en[RSZ_B] = ENABLE; 737 RSZ_B, ENABLE); [all...] |
/drivers/net/wireless/ti/wl1251/ |
H A D | reg.h | 62 #define ENABLE (REGISTERS_BASE + 0x5450) macro 291 #define REG_ENABLE_TX_RX (ENABLE)
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H A D | boot.c | 64 wl1251_reg_write32(wl, ENABLE, 0x0);
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/drivers/scsi/aic7xxx/ |
H A D | aic7770.c | 257 ahc_outb(ahc, BCTL, ENABLE); 267 ahc_outb(ahc, BCTL, ENABLE);
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H A D | aic7xxx.reg | 740 field ENABLE 0x01
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H A D | aic7xxx_reg.h_shipped | 590 #define ENABLE 0x01
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/drivers/net/plip/ |
H A D | plip.c | 128 #define ENABLE(irq) if (irq != -1) enable_irq(irq) macro 612 ENABLE(dev->irq); 686 ENABLE(dev->irq); 692 ENABLE(dev->irq); 790 ENABLE(dev->irq); 854 ENABLE(dev->irq); 892 ENABLE(dev->irq);
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/drivers/char/ |
H A D | dsp56k.c | 60 #define handshake(count, maxio, timeout, ENABLE, f) \ 66 for (t = 0; t < timeout && !ENABLE; t++) \ 68 if(!ENABLE) \
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/drivers/gpu/drm/radeon/ |
H A D | rv6xxd.h | 197 # define ENABLE (1 << 0) macro
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H A D | nid.h | 707 #define ENABLE (1 << 0) macro
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/drivers/input/serio/ |
H A D | gscps2.c | 52 #define ENABLE 1 macro 308 gscps2_enable(ps2port, ENABLE);
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/drivers/video/fbdev/ |
H A D | stifb.c | 176 #define ENABLE 1 /* for enabling/disabling screen */ macro 764 case ENABLE: 982 int enable = (blank_mode == 0) ? ENABLE : DISABLE; 1027 hyperResetPlanes(fb, ENABLE);
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/drivers/net/ethernet/broadcom/ |
H A D | sb1250-mac.c | 348 #define ENABLE 1 macro 1162 if (sc->rx_hw_checksum == ENABLE) { 1757 sc->rx_hw_checksum = ENABLE; 2287 if (sc->rx_hw_checksum == ENABLE)
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/drivers/pci/hotplug/ |
H A D | ibmphp_core.c | 583 case ENABLE: 1026 rc = validate(slot_cur, ENABLE);
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H A D | ibmphp.h | 679 #define ENABLE 1 macro
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/drivers/scsi/isci/ |
H A D | registers.h | 561 (SCU_UFQGP_GEN_BIT(ENABLE) | value) 564 (~SCU_UFQGP_GEN_BIT(ENABLE) & value)
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H A D | phy.c | 530 enable_spinup |= SCU_ENSPINUP_GEN_BIT(ENABLE); 1196 enable_spinup_value &= ~SCU_ENSPINUP_GEN_BIT(ENABLE);
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H A D | port.c | 1444 pts_control_value |= SCU_PTSxCR_GEN_BIT(ENABLE) | SCU_PTSxCR_GEN_BIT(SUSPEND); 1454 ~(SCU_PTSxCR_GEN_BIT(ENABLE) | SCU_PTSxCR_GEN_BIT(SUSPEND));
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H A D | host.c | 562 SMU_CQGR_GEN_BIT(ENABLE) | 772 | (SMU_CQGR_GEN_BIT(ENABLE))
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/drivers/regulator/ |
H A D | lp8788-ldo.c | 88 #define ENABLE GPIOF_OUT_INIT_HIGH macro
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/drivers/net/ethernet/chelsio/cxgb4/ |
H A D | t4_regs.h | 440 #define ENABLE (1U << 30) macro
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H A D | t4_hw.c | 152 u32 req = ENABLE | FUNCTION(adap->fn) | reg; 160 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a 162 * ENABLE is 0 so a simple register write is easier than a
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/drivers/pinctrl/ |
H A D | pinctrl-palmas.c | 337 FUNCTION_GROUP(enable, ENABLE)
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/drivers/gpu/drm/nouveau/core/engine/graph/ |
H A D | ctxnv50.c | 182 cp_set (ctx, XFER_SWITCH, ENABLE); 962 dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_PTSZ.ENABLE */
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