Searched refs:INT_ENABLE (Results 1 - 9 of 9) sorted by relevance

/drivers/thermal/st/
H A Dst_thermal.h27 INT_ENABLE, enumerator in enum:st_thermal_regfield_ids
H A Dst_thermal_memmap.c38 [INT_ENABLE] = REG_FIELD(STIH416_MPE_INT_EN, 0, 0),
69 reg_fields[INT_ENABLE]);
/drivers/rtc/
H A Drtc-spear.c68 #define INT_ENABLE (1<<31) /* interrupt enable */ macro
105 if (!(val & INT_ENABLE)) {
107 val |= INT_ENABLE;
117 if (val & INT_ENABLE) {
118 val &= ~INT_ENABLE;
279 alm->enabled = readl(config->ioaddr + CTRL_REG) & INT_ENABLE;
/drivers/uio/
H A Duio_aec.c36 #define INT_ENABLE 0x10 macro
116 iowrite32(INT_ENABLE, info->priv + INT_ENABLE_ADDR);
/drivers/watchdog/
H A Dsp805_wdt.c43 #define INT_ENABLE (1 << 0) macro
145 writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base +
/drivers/net/ethernet/icplus/
H A Dipg.c692 IPG_IE_RX_DMA_COMPLETE | IPG_IE_RX_DMA_PRIORITY), INT_ENABLE);
1677 IPG_IE_LINK_EVENT | IPG_IE_UPDATE_STATS, INT_ENABLE);
1737 ipg_w16(0x0000, INT_ENABLE);
1824 } while (ipg_r16(INT_ENABLE) & IPG_IE_RSVD_MASK);
H A Dipg.h74 INT_ENABLE = 0x5c, enumerator in enum:ipg_regs
/drivers/input/misc/
H A Dadxl34x.c42 #define INT_ENABLE 0x2E /* R/W Interrupt enable control */ macro
63 /* INT_ENABLE/INT_MAP/INT_SOURCE Bits */
881 AC_WRITE(ac, INT_ENABLE, ac->int_mask | OVERRUN);
/drivers/mtd/nand/
H A Ddenali.c559 uint16_t INT_ENABLE)
564 if (INT_ENABLE)
558 denali_set_intr_modes(struct denali_nand_info *denali, uint16_t INT_ENABLE) argument

Completed in 234 milliseconds