Searched refs:NV03_PFIFO_CACHE1_PUSH1 (Results 1 - 5 of 5) sorted by relevance

/drivers/gpu/drm/nouveau/core/engine/fifo/
H A Dnv04.c214 chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max;
236 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max);
520 chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max;
636 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max);
H A Dnv04.h37 #define NV03_PFIFO_CACHE1_PUSH1 0x00003204 macro
H A Dnv17.c200 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max);
H A Dnv40.c341 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max);
/drivers/gpu/drm/nouveau/
H A Dnouveau_reg.h471 #define NV03_PFIFO_CACHE1_PUSH1 0x00003204 macro

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