Searched refs:NV03_PFIFO_INTR_0 (Results 1 - 5 of 5) sorted by relevance

/drivers/gpu/drm/nouveau/core/engine/fifo/
H A Dnv04.c334 nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
446 nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
515 while ((status = nv_rd32(priv, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) {
537 nv_wr32(priv, NV03_PFIFO_INTR_0,
563 nv_wr32(priv, NV03_PFIFO_INTR_0, status);
638 nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff);
H A Dnv04.h9 #define NV03_PFIFO_INTR_0 0x00002100 macro
H A Dnv17.c202 nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff);
H A Dnv40.c343 nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff);
/drivers/gpu/drm/nouveau/
H A Dnouveau_reg.h443 #define NV03_PFIFO_INTR_0 0x00002100 macro

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