Searched refs:OUT_RING (Results 1 - 25 of 33) sorted by relevance

12

/drivers/gpu/drm/nouveau/
H A Dnvc0_fbcon.c43 OUT_RING (chan, 1);
48 OUT_RING (chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
50 OUT_RING (chan, rect->color);
52 OUT_RING (chan, rect->dx);
53 OUT_RING (chan, rect->dy);
54 OUT_RING (chan, rect->dx + rect->width);
55 OUT_RING (chan, rect->dy + rect->height);
58 OUT_RING (chan, 3);
77 OUT_RING (chan, 0);
79 OUT_RING (cha
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H A Dnv50_fbcon.c43 OUT_RING(chan, 1);
48 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
50 OUT_RING(chan, rect->color);
52 OUT_RING(chan, rect->dx);
53 OUT_RING(chan, rect->dy);
54 OUT_RING(chan, rect->dx + rect->width);
55 OUT_RING(chan, rect->dy + rect->height);
58 OUT_RING(chan, 3);
77 OUT_RING(chan, 0);
79 OUT_RING(cha
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H A Dnv04_fbcon.c42 OUT_RING(chan, (region->sy << 16) | region->sx);
43 OUT_RING(chan, (region->dy << 16) | region->dx);
44 OUT_RING(chan, (region->height << 16) | region->width);
62 OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3);
66 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
68 OUT_RING(chan, rect->color);
70 OUT_RING(chan, (rect->dx << 16) | rect->dy);
71 OUT_RING(chan, (rect->width << 16) | rect->height);
109 OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff));
110 OUT_RING(cha
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H A Dnvc0_fence.c37 OUT_RING (chan, upper_32_bits(virtual));
38 OUT_RING (chan, lower_32_bits(virtual));
39 OUT_RING (chan, sequence);
40 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
41 OUT_RING (chan, 0x00000000);
53 OUT_RING (chan, upper_32_bits(virtual));
54 OUT_RING (chan, lower_32_bits(virtual));
55 OUT_RING (chan, sequence);
56 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL |
H A Dnouveau_bo.c579 OUT_RING (chan, handle & 0x0000ffff);
593 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
594 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
595 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
596 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
597 OUT_RING (chan, PAGE_SIZE);
598 OUT_RING (chan, PAGE_SIZE);
599 OUT_RING (chan, PAGE_SIZE);
600 OUT_RING (chan, new_mem->num_pages);
612 OUT_RING (cha
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H A Dnv17_fence.c53 OUT_RING (prev, fctx->sema.handle);
54 OUT_RING (prev, 0);
55 OUT_RING (prev, value + 0);
56 OUT_RING (prev, value + 1);
62 OUT_RING (chan, fctx->sema.handle);
63 OUT_RING (chan, 0);
64 OUT_RING (chan, value + 1);
65 OUT_RING (chan, value + 2);
H A Dnouveau_dma.h102 OUT_RING(struct nouveau_channel *chan, int data) function
113 OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd);
119 OUT_RING(chan, 0x40000000 | (subc << 13) | (size << 18) | mthd);
125 OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2));
131 OUT_RING(chan, 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2));
137 OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2));
H A Dnv84_fence.c44 OUT_RING (chan, chan->vram.handle);
46 OUT_RING (chan, upper_32_bits(virtual));
47 OUT_RING (chan, lower_32_bits(virtual));
48 OUT_RING (chan, sequence);
49 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
50 OUT_RING (chan, 0x00000000);
62 OUT_RING (chan, chan->vram.handle);
64 OUT_RING (chan, upper_32_bits(virtual));
65 OUT_RING (chan, lower_32_bits(virtual));
66 OUT_RING (cha
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H A Dnv04_fence.c44 OUT_RING (chan, fence->base.seqno);
H A Dnv10_fence.c36 OUT_RING (chan, fence->base.seqno);
H A Dnv50_display.c539 OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
540 OUT_RING (chan, sync->addr ^ 0x10);
542 OUT_RING (chan, sync->data + 1);
544 OUT_RING (chan, sync->addr);
545 OUT_RING (chan, sync->data);
554 OUT_RING (chan, chan->vram.handle);
556 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
557 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
558 OUT_RING (chan, sync->data + 1);
559 OUT_RING (cha
[all...]
/drivers/gpu/drm/r128/
H A Dr128_state.c49 OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3));
50 OUT_RING(boxes[0].x1);
51 OUT_RING(boxes[0].x2 - 1);
52 OUT_RING(boxes[0].y1);
53 OUT_RING(boxes[0].y2 - 1);
58 OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3));
59 OUT_RING(boxes[1].x1);
60 OUT_RING(boxes[1].x2 - 1);
61 OUT_RING(boxes[1].y1);
62 OUT_RING(boxe
[all...]
H A Dr128_drv.h466 OUT_RING(CCE_PACKET0(R128_WAIT_UNTIL, 0)); \
467 OUT_RING(R128_EVENT_CRTC_OFFSET); \
525 #define OUT_RING(x) do { \ macro
527 DRM_INFO(" OUT_RING( 0x%08x ) at 0x%x\n", \
/drivers/gpu/drm/radeon/
H A Dr600_blit.c95 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
96 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
97 OUT_RING(gpu_addr >> 8);
98 OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
99 OUT_RING(2 << 0);
102 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
103 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
104 OUT_RING(gpu_addr >> 8);
107 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
108 OUT_RING((R600_CB_COLOR0_SIZ
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H A Dradeon_state.c458 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
459 OUT_RING((box->y1 << 16) | box->x1);
460 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
461 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1));
490 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6));
491 OUT_RING(ctx->pp_misc);
492 OUT_RING(ctx->pp_fog_color);
493 OUT_RING(ctx->re_solid_color);
494 OUT_RING(ctx->rb3d_blendcntl);
495 OUT_RING(ct
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H A Dr300_cmdbuf.c75 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1));
107 OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) |
109 OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) |
121 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1));
122 OUT_RING(0);
123 OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK);
148 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
149 OUT_RING(R300_RB3D_DC_FLUSH);
152 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
153 OUT_RING(RADEON_WAIT_3D_IDLECLEA
[all...]
H A Dradeon_drv.h1930 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1931 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1936 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1937 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1942 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1943 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1949 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1950 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1955 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1956 OUT_RING(RADEON_RB3D_DC_FLUS
2103 #define OUT_RING macro
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H A Dr600_cp.c2313 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
2314 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
2316 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
2317 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
2318 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
2335 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
2336 OUT_RING(0x00000001);
2338 OUT_RING(0x00000003);
2340 OUT_RING(0x00000000);
2341 OUT_RING((dev_pri
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/drivers/gpu/drm/i810/
H A Di810_dma.c465 OUT_RING(GFX_OP_COLOR_FACTOR);
466 OUT_RING(code[I810_CTXREG_CF1]);
468 OUT_RING(GFX_OP_STIPPLE);
469 OUT_RING(code[I810_CTXREG_ST1]);
476 OUT_RING(tmp);
483 OUT_RING(0);
497 OUT_RING(GFX_OP_MAP_INFO);
498 OUT_RING(code[I810_TEXREG_MI1]);
499 OUT_RING(code[I810_TEXREG_MI2]);
500 OUT_RING(cod
[all...]
/drivers/gpu/drm/msm/
H A Dmsm_ringbuffer.h36 OUT_RING(struct msm_ringbuffer *ring, uint32_t data) function
/drivers/gpu/drm/msm/adreno/
H A Da3xx_gpu.c47 OUT_RING(ring, 0x000003f7);
48 OUT_RING(ring, 0x00000000);
49 OUT_RING(ring, 0x00000000);
50 OUT_RING(ring, 0x00000000);
51 OUT_RING(ring, 0x00000080);
52 OUT_RING(ring, 0x00000100);
53 OUT_RING(ring, 0x00000180);
54 OUT_RING(ring, 0x00006600);
55 OUT_RING(ring, 0x00000150);
56 OUT_RING(rin
[all...]
H A Dadreno_gpu.c137 OUT_RING(ring, submit->cmd[i].iova);
138 OUT_RING(ring, submit->cmd[i].size);
152 OUT_RING(ring, submit->fence);
160 OUT_RING(ring, HLSQ_FLUSH);
163 OUT_RING(ring, 0x00000000);
167 OUT_RING(ring, CACHE_FLUSH_TS);
168 OUT_RING(ring, rbmemptr(adreno_gpu, fence));
169 OUT_RING(ring, submit->fence);
173 OUT_RING(ring, 0x80000000);
179 OUT_RING(rin
[all...]
H A Dadreno_gpu.h156 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
164 OUT_RING(ring, CP_TYPE2_PKT);
171 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
/drivers/gpu/drm/i915/
H A Di915_dma.c58 #define OUT_RING(x) \ macro
385 OUT_RING(buffer[i]);
387 OUT_RING(0);
414 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
415 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
416 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
417 OUT_RING(DR4);
423 OUT_RING(GFX_OP_DRAWRECT_INFO);
424 OUT_RING(DR1);
425 OUT_RING((bo
[all...]
/drivers/video/fbdev/intelfb/
H A Dintelfbhw.c1552 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1553 OUT_RING(MI_NOOP);
1690 OUT_RING(br00);
1691 OUT_RING(br13);
1692 OUT_RING(br14);
1693 OUT_RING(br09);
1694 OUT_RING(br16);
1695 OUT_RING(MI_NOOP);
1739 OUT_RING(br00);
1740 OUT_RING(br1
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